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TDP0604 Datasheet(PDF) 13 Page - Texas Instruments |
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TDP0604 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 65 page  6.6 Timing Requirements (continued) MIN NOM MAX UNIT tSU_DAT Data setup time 50 ns tR Rise time of both SDA and SCL signals 120 ns tF Fall time of both SDA and SCL signals 4 120 ns tSU_STO Setup time for STOP condition 0.26 μs DDC Snoop I2C Timings. Refer to Figure 7-9. fSCL I2C DDC clock frequency 100 kHz tBUF Bus free time between START and STOP conditions 4.7 µs tHD_STA Hold time after repeated START condition. After this period, the first clock pulse is generated 4 µs tLOW Low period of the I2C clock 4.7 µs tHIGH High period of the I2C clock 4 µs tSU_STA Setup time for a repeated START condition 4.7 µs tHD_DAT Data hold time 0 μs tSUDAT Data setup time 250 ns tR Rise time of both SDA and SCL signals. Measured from 30% to 70%. 1000 ns tF Fall time of both SDA and SCL signals Measured from 70% to 30%. 300 ns tSU_STO Setup time for STOP condition 4 μs Cb_LV Capacitive load for each bus line on LV side 50 pF Power-On. Refer to Figure 7-1. tVCC_RAMP VCC supply ramp. Measured from 10% to 90%. 0.10 50 ms tD_PG Internal POR de-assertion delay 5 ms tVIO_SU VIO supply stable before reset(2) high. 100 µs tCFG_SU Configuration pins(1) setup before reset(2) high. 0 µs tCFG_HD Configuration pins(1) hold after reset(2)high. 500 µs (1) Follow comprise the configuration pins: MODE, ADDR/EQ0, EQ1, TXSWG, TXSLEW, TXPRE, AC_EN, HPDOUT_SEL, DCGAIN (2) Reset is the logical AND of internal POR and EN pin. 6.7 Switching Characteristics over recommended voltage and operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Redriver fHDMI14_o pen Maximum HDMI 1.4 clock frequency at which TX termination is guarenteed to be open HDMI1.4; 25MHz ≤ IN_CLK ≤ 340MHz; TXTERM_AUTO_HDMI14 = 0h; TERM = 2h; TX is DC-coupled; 165 MHz fHDMI14_3 00 Minimum HDMI 1.4 clock frequency at which TX termination is guarenteed to be 300-ohms HDMI1.4; 25MHz ≤ IN_CLK ≤ 340MHz; TXTERM_AUTO_HDMI14 = 0h; TERM = 2h; TX is DC-coupled; 250 MHz tPD Propagation delay time At TTP4; 90 220 ps tSK1(T) Clock lane Intra-pair output skew with zero intra-pair skew at inputs At TTP4; No intra-pair skew at input; 6Gbps with 150 MHz clock; TX termination 100-Ω; Limited mode; 0.10 0.15 UI tSK1(T) Data lane Intra-pair output skew with zero intra-pair skew at inputs At TTP4; No intra-pair skew at input; At 6Gbps; TX termination 100-Ω; Limited mode; 0.035 0.09 UI tSK2(T) Inter-pair output skew At TTP4; At 6Gbps; 30 ps tRF-CLK-14 Transition time (rise and fall time) for clock lane when operating at HDMI1.4 At TTP4; 20% to 80%; Clock Frequency = 300 MHz; 75 600 ps www.ti.com TDP0604 SLLSFJ8 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TDP0604 |
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