TDP0604 datasheet(11/65 Pages) TI

11 / 65 page

6.5 Electrical Characteristics (continued)

over recommended voltage and operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VRX_ASSE

Signal detect assert level.

PRBS7 pattern; 6 Gbps;

150

mVpp

VRX_DEAS

SERT

Signal detect deassert level.

PRBS7 pattern; 6 Gbps;

mVpp

VICM-DC

Input DC common mode voltage bias

At pins;

2.5

3.3

VCC

EEQ_6Gbs

_MAX_LT

Maximum Fixed EQ gain (AC - DC)

At 3 GHz; 6Gbps CTLE; EQ15; DC Gain

= 0dB; Limited Mode; At output of RX;

12.0

EEQ_6Gbp

s_MIN_LT

Minimum Fixed EQ gain (AC - DC)

At 3 GHz; 6Gbps CTLE; EQ0; DC Gain =

0dB; Limited Mode; At output of RX;

0.6

EEQ_6Gbp

s_BYPASS_

Maximum Fixed EQ Gain when EQ is

bypassed. (AC - DC)

At 3GHz; 6Gbps CTLE; DC Gain = 0dB;

Limited Mode; At output of RX;

-2.0

EEQ_3Gbs

_MAX_LT

Maximum Fixed EQ gain (AC - DC)

At 1.5 GHz; 3Gbps CTLE; EQ15; DC

Gain = 0dB; Limited Mode; At output of

RX;

EEQ_3Gbp

s_MIN_LT

Minimum Fixed EQ gain (AC - DC)

At 1.5 GHz; 3Gbps CTLE; EQ0; DC Gain

= 0dB; Limited Mode; At output of RX;

0.8

RINT

Input differential impedance when

termination is enabled

At TTP2; HPD_IN = H;

100

115

HDMI HIGH SPEED OUTPUTS (Limited Mode)

VOL_open

Single-ended low-level output voltage for

DR ≤ 1.65 Gbps data rate

DR = 270 Mbps; HPD_IN = H; AC_EN =

L (DC-coupled); TXSWG = "F" (1000mV);

TXPRE = "F" (0dB); TX termination

open; VCC_EXT = 3.3V; 25

℃ ≤ Ta ≤

℃;

2.7

2.9

VOL_300

Single-ended low-level output voltage

1.65 Gbps < DR ≤ 3.4 Gbps.

DR = 3.4 Gbps; HPD_IN = H; AC_EN =

L (DC-coupled); TXSWG = "F" (1000mV);

TXPRE = "F" (0dB); TX termination 300-

ohms; VCC_EXT = 3.3V; 25

℃ ≤ Ta ≤

℃;

2.6

2.9

VOL_DAT2

Data lane single-ended low-level output

voltage 3.4 Gbps < DR ≤ 6 Gbps.

DR = 5.94 Gbps; HPD_IN = H; AC_EN =

L (DC-coupled); TXSWG = "F" (1000mV);

TXPRE = "F" (0dB); VCC_EXT =

3.3V; 25

℃ ≤ Ta ≤ 85℃;

2.3

2.9

VSWING_D

A_14

Single-ended output voltage swing on

data lanes with TX term set to open.

DR = 1.5 Gbps; HPD_IN = H; AC_EN =

L (DC-coupled); TXSWG = "F" (1000mV);

TXPRE = "F" (0dB); VCC_EXT =

3.3V; 25

℃ ≤ Ta ≤ 85℃;

400

500

600

VSWING_D

A_14

Single-ended output voltage swing on

data lanes with TX term set to 300-ohms.

DR = 3.4 Gbps;HPD_IN = H; AC_EN = L

(DC-coupled); TXSWG = "F" (1000mV);

TXPRE = "F" (0dB); VCC_EXT =

3.3V; 25

℃ ≤ Ta ≤ 85℃;

400

500

600

VSWING_D

A_20

Single-ended output voltage swing on

data lanes for HDMI2.0 operation.

DR = 5.94 Gbps;HPD_IN = H; AC_EN =

L (DC-coupled); TXSWG = "F" (1000mV);

TXPRE = "F" (0dB); VCC_EXT =

3.3V; 25

℃ ≤ Ta ≤ 85℃;

400

500

600

VSWING_C

LK_14_OPE

Single-ended output voltage swing on

clock lane for DR ≤ 3.4 Gbps datarate

HPD_IN = H; AC_EN = L (DC-coupled);

TXSWG = "F" (1000mV); TXPRE = "F"

(0dB); VCC_EXT = 3.3V; 25

℃ ≤ Ta ≤

℃; TERM set to open;

400

500

600

VSWING_C

LK_20

Single-ended output voltage swing on

clock lane for HDMI 2.0

HPD_IN = H; AC_EN = L (DC-coupled);

TXSWG = "F" (1000mV); TXPRE = "F"

(0dB); VCC_EXT = 3.3V; 25

℃ ≤ Ta ≤

℃;

300

400

600

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TDP0604

SLLSFJ8 – DECEMBER 2021

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