TDP0604 datasheet(12/65 Pages) TI

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6.5 Electrical Characteristics (continued)

over recommended voltage and operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOD_3G

Data lanes Differential output swing

At TTP4; 2.97Gbps; HPD_IN = H; AC_EN

= L or H; TXSWG = "F" (1000mV);

TXPRE = "F" (0dB); 25

℃ ≤ Ta ≤ 85℃;

400

1560

VOD_6G

Data lanes Differential output swing

At TTP4_EQ; 5.94Gbps; HPD_IN = H;

AC_EN = L or H; TXSWG = "F"

(1000mV); TXPRE = "F" (0dB); 25

℃ ≤

Ta ≤ 85

℃;

150

1560

ILEAK

Failsafe condition leakage current

VCC = 0 V; DC-coupled; TMDS output

pulled to 3.465 V with 50 ohm resistors

µA

IOS

Short circuit current limit

OUT_CLK, OUT_D[2:0] outputs P or N

shorted to GND

RTERM14

Internal termination for DR ≤ 3.4 Gbps

when DC-coupled

TERM = 1h; AC_EN = L (DC-

coupled);HPD_IN=H; Active State; 25

℃ ≤

TA ≤ 85℃;

235

295

375

RTERM14

Internal termination for DR ≤ 3.4 Gbps

when AC-coupled

TERM = 1h; AC_EN = H (AC-

coupled); HPD_IN=H; Active State; 25

℃

≤ TA ≤ 85℃;

235

295

375

RTERM2+

Internal termination for DR > 3.4 Gbps

when DC-coupled.

TERM = 3h; AC_EN = L (DC-

coupled);HPD_IN=H; Active State; 25

℃ ≤

TA ≤ 85℃;

100

115

RTERM2+

Internal termination for DR > 3.4 Gbps

when AC-coupled.

TERM = 3h; AC_EN = H (AC-

coupled); HPD_IN=H; Active State; 25

℃

≤ TA ≤ 85℃;

100

115

VTXPRE0-

RATIO

Transmitter FFE pre-emphasis ratio for

0dB.

TERM = 3h; HPD_IN = H; TX_AC_EN

= 0; CLK_VOD = 3h; D0_TXFFE = 0h;

D0_VOD = 3h; D1_TXFFE = 0h; D1_VOD

= 3h; D2_TXFFE = 0h; D2_VOD = 3h; 20

* log (Vp/Vn); 128 zeros followed by 128

ones;

VTXPRE1-

RATIO

Transmitter FFE pre-emphasis ratio for

3.5dB for data lanes

At 5.94Gbps HDMI 2.0; TERM = 3h;

HPD_IN = H; TX_AC_EN = 0; CLK_VOD

= 3h; D0_TXFFE = 1h; D0_VOD =

3h; D1_TXFFE = 1h; D1_VOD = 3h;

D2_TXFFE = 1h; D2_VOD = 3h; 20 * log

(Vp/Vn); 128 zeros followed by 128 ones;

4.0

VTXPRE2-

RATIO

Transmitter FFE pre-emphasis ratio for

6dB for data lanes

At 5.94Gbps HDMI 2.0; TERM = 3h;

HPD_IN = H; TX_AC_EN = 0; CLK_VOD

= 3h; D0_TXFFE = 2h; D0_VOD =

3h; D1_TXFFE = 2h; D1_VOD = 3h;

D2_TXFFE = 2h; D2_VOD = 3h; 20 * log

(Vp/Vn); 128 zeros followed by 128 ones;

6.5

6.6 Timing Requirements

MIN

NOM

MAX

UNIT

Local I2C (SCL/CFG0, SDA/CFG1). Refer to Figure 7-9.

fSCL

I2C clock frequency

MHz

tBUF

Bus free time between START and STOP conditions

0.5

µs

tHD_STA

Hold time after repeated START condition. After this period, the first clock

pulse is generated

0.26

µs

tLOW

Low period of the I2C clock

0.5

µs

tHIGH

High period of the I2C clock

0.26

µs

tSU_STA

Setup time for a repeated START condition

0.26

µs

tHD_DAT

Data hold time

μs

TDP0604

SLLSFJ8 – DECEMBER 2021

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