TDP0604 datasheet(7/65 Pages) TI

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6.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

TDP0604I Ambient temperature

–40

°C

6.4 Thermal Information

THERMAL METRIC(1)

TDP0604

UNIT

RNQ (WQFN)

40 PINS

RθJA

Junction-to-ambient thermal resistance

30.9

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

21.2

°C/W

RθJB

Junction-to-board thermal resistance

11.7

°C/W

ΨJT

Junction-to-top characterization parameter

0.3

°C/W

ΨJB

Junction-to-board characterization parameter

11.7

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

3.8

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

over recommended voltage and operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER

PACTIVE-

H14-LT-

ARX-DTX

Power dissipation in HDMI 1.4 3.4 Gbps

active operation

Pin Strap mode; DR = 3.4Gbps; HPD_IN

= H; No de-emphasis/pre-emphasis;

Limited redriver mode; DC-coupled TX;

AC-coupled RX; 3GbpsCTLE;

190

PACTIVE-

H20-LT-

ARX-DTX

Power dissipation in HDMI 2.0 6 Gbps

active operation

Pin Strap mode; DR = 6Gbps; HPD_IN

= H; No de-emphasis/pre-emphasis;

Limited redriver mode; DC-coupled TX;

AC-coupled RX; 6GbpsCTLE;

215

PPD

Power in power-down (HPD_IN = L)

Pin Strap mode; HPD_IN = L; EN = L or

H; High-speed outputs are disconnected;

0.55

PSD

Power in standby (HPD_IN = H) but no

incoming signal with DDC Buffer disabled

Pin Strap mode; HPD_IN = H; No

incoming signal; EN = H; DC-coupled TX;

AC-coupled RX; Limited redriver mode;

High-speed outputs are connected;

1.0

PSD

Power in standby (HPD_IN = H) but no

incoming signal with DDC buffer enabled.

Pin Strap mode; HPD_IN = H; No

incoming signal; EN = H; DC-coupled TX;

AC-coupled RX; Limited redriver mode;

High-speed outputs are connected;

1.2

IVIOQ

VIO quiescent current

HPD_IN = H;VCC = VIO = 3.6V;

LV_DDC_SDA/SCL = H;

µA

IVIOA

VIO active instantaneous current

VCC = VIO = 3.6V; HPD_IN = H;

2-LEVEL CONTROL PINS (EN, SCL/CFG0, SDA/CFG1, AC_EN)

VIO_TRSH

Threshold for selecting between 1.2-V

LVCMOS / 1.8-V LVCMOS

1.5

VIO_TRSH

Threshold for selecting between 1.8-V

LVCMOS / 3.3-V LVCMOS

2.5

VIL_1p2V

Low-level input voltage for SCL/CFG0,

SDA/CFG1

VIO = 1.26V; VCC = 3.0V;

-0.3

0.378

VIH_1p2V

High-level input voltage for SCL/CFG0,

SDA/CFG1

VIO = 1.14V; VCC = 3.6V;

0.8

3.6

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TDP0604

SLLSFJ8 – DECEMBER 2021

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