AM625 datasheet(103/235 Pages) TI

103 / 235 page

7.10.2.2.2 Power-Down Sequencing

Figure 7-6 describes the device power-down sequencing.

AM64x_ELCH_02

MCU_PORz

MCU_OSC0_XI, MCU_OSC0_XO

VSYS

VMON_VSYS

VSYS, VMON_VSYS

VPP

VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,

(1)

VDDSHV4 , VDDSHV5 , VDDSHV6 , VDDSHV_CANUART , VDDA_3P3_USB,

(1)

VMON_3P3_SOC

VDDS_OSC0, VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,

(2)

VDDSHV4 , VDDSHV5 , VDDSHV6 , VDDSHV_CANUART , VDDA_MCU,

(2)

VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_1P8_CSIRX0, VDDA_1P8_OLDI0,

VDDA_1P8_USB, VMON_1P8_SOC, VDDA_TEMP0, VDDA_TEMP1,

VDDS_DDR, VDDS_DDR_C

VDD_CORE

, VDD_CANUART , VDDA_CORE_CSIRX0 , VDDA_CORE_USB ,

(3)(5)

(3)

VDDA_DDR_PLL0

(6)

VDD_CORE

, VDDR_CORE , VDDA_CANUART , VDDA_CORE_CSIRX0 ,

(5)

(4)(5)

(4)

(6)

VDDA_CORE_USB ,VDDA_DDR_PLL0

Hi-Z

Figure 7-6. Power-Down Sequencing

1. VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-6] when operating at 3.3V.

2. VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-6] when operating at 1.8V.

3. VDD_CORE, VDD_CANUART, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 when

operating at 0.75V.

4. VDD_CORE, VDD_CANUART, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 when

operating at 0.85V.

5. The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE +

0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after

VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirements

beyond the one defined for VDDR_CORE. VDD_CORE and VDDR_CORE are expected to be powered by

the same source so they ramp together when VDD_CORE is operating at 0.85V.

6. VDDA_DDR_PLL0 is connected to VDD_CORE inside the ALW package.

7.10.3 System Timing

For more details about features and additional description information on the subsystem multiplexing signals,

see the corresponding subsections within Signal Descriptions and Detailed Description sections.

Table 7-4. System Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.5

2 V/ns

www.ti.com

AM625, AM623

SPRSP58 – JUNE 2022

Submit Document Feedback

103

Product Folder Links: AM625 AM623

AM625 Datasheet(PDF) 103 Page - Texas Instruments

AM625 Datasheet(HTML) 103 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL