AM625 datasheet(104/235 Pages) TI

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Table 7-4. System Timing Conditions (continued)

PARAMETER

MIN

MAX

UNIT

OUTPUT CONDITIONS

Output load capacitance

30 pF

7.10.3.1 Reset Timing

Tables and figures provided in this section define timing requirements and switching characteristics for reset

related signals.

Table 7-5. MCU_PORz Timing Requirements

see Figure 7-7

NO.

PARAMETER

MIN

MAX UNIT

RST1

th(SUPPLIES_VALID - MCU_PORz)

Hold time, MCU_PORz active (low) at Power-up

after supplies valid (using external crystal)

9500000

RST2

Hold time, MCU_PORz active (low) at Power-up

after supplies valid and external clock stable (using

external LVCMOS oscillator)

1200

RST3

tw(MCU_PORzL)

Pulse Width minimum, MCU_PORz low after

Power-up (without removal of Power or system

reference clock MCU_OSC0_XI/XO)

1200

Figure 7-7. MCU_PORz Timing Requirements

Table 7-6. MCU_RESETSTATz, and RESETSTATz Switching Characteristics

see Figure 7-8

NO.

PARAMETER

MIN

MAX UNIT

RST4

td(MCU_PORzL-MCU_RESETSTATzL)

Delay time, MCU_PORz active (low) to

MCU_RESETSTATz active (low)

RST5

td(MCU_PORzH-MCU_RESETSTATzH)

Delay time, MCU_PORz inactive (high) to

MCU_RESETSTATz inactive (high)

6120*S(1)

RST6

td(MCU_PORzL-RESETSTATzL)

Delay time, MCU_PORz active (low) to

RESETSTATz active (low)

RST7

td(MCU_PORzH-RESETSTATzH)

Delay time, MCU_PORz inactive (high) to

RESETSTATz inactive (high)

9195*S(1)

RST8

tw(MCU_RESETSTATzL)

Pulse Width Minimum MCU_RESETSTATz low

(SW_MCU_WARMRST)

4040*S(1)

AM625, AM623

SPRSP58 – JUNE 2022

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