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Table 7-33. RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode

see Figure 7-30

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

RGMII9 tosu(TD-TXC)

Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC

high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.2

tosu(TX_CTL-TXC)

Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC

high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.2

RGMII10 toh(TXC-TD)

Output hold time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC

high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.2

toh(TXC-TX_CTL)

Output hold time, RGMII[x]_TX_CTL valid after

RGMII[x]_TXC high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.2

RGMII[x]_TXC

(A)

RGMII[x]_TD[3:0]

(B)

RGMII[x] TX_CTL

(B)

RGMII9

1st Half-byte

TXERR

TXEN

2nd Half-byte

RGMII7

RGMII8

RGMII6

RGMII10

TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.

Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of

RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of

RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.

Figure 7-30. CPSW3G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics

- RGMII Mode

7.10.5.2 CPTS

Table 7-34, Table 7-35, Figure 7-31, Table 7-36, and Figure 7-32 present timing conditions, requirements, and

switching characteristics for CPTS.

Table 7-34. CPTS Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.5

V/ns

OUTPUT CONDITIONS

Output load capacitance

Table 7-35. CPTS Timing Requirements

see Figure 7-31

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tw(HWTSPUSHH)

Pulse duration, HWnTSPUSH high

12P(1) + 2

tw(HWTSPUSHL)

Pulse duration, HWnTSPUSH low

12P(1) + 2

tc(RFT_CLK)

Cycle time, RFT_CLK

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SPRSP58 – JUNE 2022

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