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AM625 Datasheet(PDF) 124 Page - Texas Instruments

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Part # AM625
Description  AM62x Sitara??Processors
PDF  235 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM625 Datasheet(HTML) 124 Page - Texas Instruments

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Table 7-35. CPTS Timing Requirements (continued)
see Figure 7-31
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
T4
tw(RFT_CLKH)
Pulse duration, RFT_CLK high
0.45T(2)
ns
T5
tw(RFT_CLKL)
Pulse duration, RFT_CLK low
0.45T(2)
ns
(1)
P = functional clock period in ns.
(2)
T = RFT_CLK cycle time in ns.
RFT_CLK
T3
T4
T5
HWn_TSPUSH
T1
T2
Figure 7-31. CPTS Timing Requirements
Table 7-36. CPTS Switching Characteristics
see Figure 7-32
NO.
PARAMETER
DESCRIPTION
SOURCE
MIN
MAX
UNIT
T6
tw(TS_COMPH)
Pulse duration, TS_COMP high
36P(1) - 2
ns
T7
tw(TS_COMPL)
Pulse duration, TS_COMP low
36P(1) - 2
ns
T8
tw(TS_SYNCH)
Pulse duration, TS_SYNC high
36P(1) - 2
ns
T9
tw(TS_SYNCL)
Pulse duration, TS_SYNC low
36P(1) - 2
ns
T10
tw(SYNC_OUTH)
Pulse duration, SYNCn_OUT high
TS_SYNC
36P(1) - 2
ns
GENF
5P(1) - 2
ns
T11
tw(SYNC_OUTL)
Pulse duration, SYNCn_OUT low
TS_SYNC
36P(1) - 2
ns
GENF
5P(1) - 2
ns
(1)
P = functional clock period in ns.
TS_COMP
T6
T7
TS_SYNC
T8
T9
SYNCn_OUT
T10
T11
Figure 7-32. CPTS Switching Characteristics
For more information, see Data Movement Architecture (DMA) chapter in the device TRM.
7.10.5.3 DDRSS
For more details about features and additional description information on the device (LP)DDR4 Memory
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 7-37 and Figure 7-33 present switching characteristics for DDRSS.
AM625, AM623
SPRSP58 – JUNE 2022
www.ti.com
124
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: AM625 AM623



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