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AM625 Datasheet(PDF) 128 Page - Texas Instruments

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Part # AM625
Description  AM62x Sitara??Processors
PDF  235 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM625 Datasheet(HTML) 128 Page - Texas Instruments

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Table 7-42. ECAP Timing Requirements
see Figure 7-36
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
CAP1
tw(CAP)
Pulse duration, CAP (asynchronous)
2P(1) + 2
ns
(1)
P = sysclk period in ns.
CAP
CAP1
EPERIPHERALS_TIMNG_01
Figure 7-36. ECAP Timings Requirements
Table 7-43. ECAP Switching Characteristics
see Figure 7-37
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
CAP2
tw(APWM)
Pulse duration, APWMx high/low
2P(1) - 2
ns
(1)
P = sysclk period in ns.
APWM
CAP2
EPERIPHERALS_TIMNG_02
Figure 7-37. ECAP Switching Characteristics
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.
7.10.5.6 Emulation and Debug
For more details about features and additional description information on the device Trace and JTAG interfaces,
see the corresponding subsections within Signal Descriptions and Detailed Description sections.
7.10.5.6.1 Trace
Table 7-44. Trace Timing Conditions
PARAMETER
MIN
MAX
UNIT
OUTPUT CONDITIONS
CL
Output load capacitance
2
5
pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch)
Propagation delay mismatch across all traces
200
ps
Table 7-45. Trace Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
1.8V Mode
DBTR1
tc(TRC_CLK)
Cycle time, TRC_CLK
6.83
ns
DBTR2
tw(TRC_CLKH)
Pulse width, TRC_CLK high
2.66
ns
DBTR3
tw(TRC_CLKL)
Pulse width, TRC_CLK low
2.66
ns
DBTR4
tosu(TRC_DATAV-
TRC_CLK)
Output setup time, TRC_DATA valid to TRC_CLK edge
0.85
ns
DBTR5
toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid
0.85
ns
DBTR6
tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge
0.85
ns
DBTR7
toh(TRC_CLK-TRC_CTLI)
Output hold time, TRC_CLK edge to TRC_CTL invalid
0.85
ns
AM625, AM623
SPRSP58 – JUNE 2022
www.ti.com
128
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Product Folder Links: AM625 AM623



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