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MEC1632 Datasheet(PDF) 211 Page - Microchip Technology |
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MEC1632 Datasheet(HTML) 211 Page - Microchip Technology |
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211 / 636 page ![]() 2012-2018 Microchip Technology Inc. DS00001592B-page 211 MEC1632 11.4.7 POWER MANAGEMENT 2 CONTROL 1 (PM2_CNTRL 1) RESERVED Reserved bits return ‘0’ when read. 11.4.8 POWER MANAGEMENT 2 CONTROL 2 (PM2_CNTRL 2) RESERVED Reserved bits return ‘0’ when read. 11.5 EC_SCI# Pin Interface The EC_SCI# pin logic hardware is shown below in Figure 11-1. Any or all of the PWRBTN, SLPBTN_STS, and RTC_ bits in the Power Management 1 Status Register 2 (PM1_STS 2) can assert the EC_SCI# pin if enabled by the PWRBTN_, SLPBTN_, and RTC_ bits in the PM1_EN 2 register. The EC_SCI_ bit can assert the EC_SCI# pin at any time, without being enabled. The EC_SCI_ bit is located in the EC_PM_STS Register. The EC_SCI_ bit is in the MEC1632 and is read/write by the EC. If the EC_SCI_ bit is “1”, an interrupt is generated on the EC_SCI# pin. TABLE 11-10: POWER MANAGEMENT 2 CONTROL REGISTER 1 (PM2_CNTRL 1) HOST OFFSET 06h 8-bit HOST SIZE EC OFFSET 106h EC SIZE POWER VTR 00h nSYS_RST DEFAULT BUS LPC SPB BYTE0 BIT D7D6 D5D4 D3D2D1 D0 HOST TYPE R R R RRR RR EC TYPE R R R RRR RR BIT NAME Reserved TABLE 11-11: POWER MANAGEMENT 2 CONTROL REGISTER 2 (PM2_CNTRL 2) HOST OFFSET 07h 8-bit HOST SIZE EC OFFSET 107h EC SIZE POWER VTR 00h nSYS_RST DEFAULT BUS LPC SPB BYTE0 BIT D7D6 D5D4 D3D2D1 D0 HOST TYPE R R R RRR RR EC TYPE R R R RRR RR BIT NAME Reserved |
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