MEC1632 datasheet(208/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 208

 2012-2018 Microchip Technology Inc.

11.4.2

POWER MANAGEMENT 1 STATUS 2 (PM1_STS 2)

Note 11-3

These bits are set/cleared by the EC directly i.e., writing ‘1’ sets the bit and writing ‘0’ clears it. These

bits can also be cleared by the Host software writing a one to this bit position and by nSYS_RST.

Writing a 0 by the Host has no effect.

Note 11-4

An interrupt (PM1_CTL2) is generated to the EC when the Host writes to this register.

PWRBTN_STS

This bit can be set or cleared by the EC to simulate a Power button status if the power is controlled by the EC. The Host

writing a one to this bit can also clear this bit. The EC must generate the associated SCI interrupt under software control.

SLPBTN_STS

This bit can be set or cleared by the EC to simulate a Sleep button status if the sleep state is controlled by the EC. The

Host writing a one to this bit can also clear this bit. The EC must generate the associated SCI interrupt under software

control.

RTC_STS

This bit can be set or cleared by the EC to simulate a RTC status. The Host writing a one to this bit can also clear this

bit. The EC must generate the associated SCI interrupt under software control.

PWRBTNOR_STS

This bit can be set or cleared by the EC to simulate a Power button override event status if the power is controlled by

the EC. The Host writing a one to this bit can also clear this bit. The EC must generate the associated hardware event

under software control.

WAK_STS

This bit can be set or cleared by the EC. The Host writing a one to this bit can also clear this bit.

TABLE 11-4:

POWER MANAGEMENT 1 STATUS REGISTER 2 (PM1_STS 2)

HOST OFFSET

8-bit HOST SIZE

EC OFFSET

101h

EC SIZE

POWER

VTR

00h nSYS_RST DEFAULT

BUS

LPC SPB

BYTE0 BIT

HOST TYPE

R/WC

EC TYPE

R/W

BIT NAME

WAK_

STS

Reserved

PWRBT-

NOR_

STS

RTC_

STS

SLPBT-

N_STS

PWRBTN

_STS

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