MEC1632 datasheet(206/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 206

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11.3.3.2

Sleep Button

The sleep button has a status and an enable bit in the PM1_BLK of registers to provide an SCI upon the button press.

The status bit is software Read/Writable by the EC; the enable bit is Read-only by the EC.

The SLPBTN_ bit is set by the Host to enable the generation of an SCI due to the sleep button event. The status bit is

set by the EC when it generates a sleep button event and is cleared by the Host writing a ‘1’ to this bit (writing a ‘0’ has

no effect); it can also be cleared by the EC. If the enable bit is set, the EC will generate an SCI power management

event.

11.3.4

RTC ALARM

The ACPI specification requires that the RTC alarm generate a hardware wake-up event from the sleeping state. The

RTC alarm can be enabled as an SCI event and its status can be determined through bits in the PM1_BLK of registers.

The status bit is software Read/Writable by the EC; the enable bit is Read-only by the EC.

The RTC_ bit is set by the Host to enable the generation of an SCI due to the RTC alarm event. The status bit is set by

the EC when the RTC generates an alarm event and is cleared by the Host writing a ‘1’ to this bit (writing a ‘0’ has no

effect); it can also be cleared by the EC. If the enable bit is set, the EC will generate an SCI power management event.

11.4

Registers

Each instance of the ACPI PM1 Block Interface has its own Logical Device Number, and Base Address as indicated in

Table 11-1.

The ACPI register model consists of a number of fixed register blocks that perform designated functions. A register block

consists of a number of registers that perform Status, Enable and Control functions. The ACPI specification deals with

events (which have an associated interrupt status and enable bits, and sometimes an associated control function) and

control features. The status registers illustrate what defined function is requesting ACPI interrupt services (SCI). Any

status bit in the ACPI specification has the following attributes:

Status bits are only set through some defined hardware or EC event.

Unless otherwise noted, status bits are cleared by the system writing a “1” to that bit position, and upon nSYS_RST.

Writing a ‘0’ has no effect.

Status bits only generate interrupts while their associated bit in the enable register is set.

Function bit positions in the status register have the same bit position in the enable register (there are exceptions to this

rule, special status bits have no enables).

Note that this implies that if the respective enable bit is reset and the hardware event occurs, the respective status bit

is set; however no interrupt is generated until the enable bit is set. This allows software to test the state of the event (by

examining the status bit) without necessarily generating an interrupt. There are a special class of status bits that have

no respective enable bit, these are called out specifically, and the respective enable bit in the enable register is marked

as reserved for these special cases.

The enable registers allow the setting of the status bit to generate an interrupt (under EC control). As a general rule,

there is an enable bit in the enable register for every status bit in the status register. The control register provides special

controls for the associated event, or special control features that are not associated with an interrupt event. The order

of a register block is the status registers, followed by enable registers, followed by control registers.

The registers in the MEC1632 ACPI PM1 Block Interface occupy eight addresses in the host I/O space and are specified

as offsets from the ACPI PM1 Block base address (Table 11-1).

TABLE 11-1:

ACPI PM1 Block Interface BASE ADDRESS TABLE

ACPI PM1 Block Interface

Instance

Table 4-1 on page 59

LDN

AHB Base Address

ACPI PM1 Block Interface

FF_1800h

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