MEC1632 datasheet(205/636 Pages) MICROCHIP

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DS00001592B-page 205

MEC1632

11.0

ACPI PM1 BLOCK INTERFACE

11.1

General Description

The MEC1632 supports ACPI as described in this section. These features comply with the ACPI Specification, Revision

1.0, through a combination of hardware and EC software.

The MEC1632 implements the ACPI fixed registers but includes only those bits that apply to the power button sleep

button and RTC alarm events. The ACPI WAK_ SLP_TYPx, and SLP_ bits are also supported.

11.2

Power, Clocks and Reset

11.2.1

POWER DOMAIN

This block is powered by VTR

See Section 7.1.1, "Power Configuration," on page 95 for details on power domains.

11.2.2

CLOCKS

This block has one clock input, the LPC Bus Clock.

See Section 7.4, "Clock Generator," on page 98 for details on clocks.

11.2.3

POWER ON RESET

This block is reset on a nSYS_RST. After nSYS_RST is asserted, all registers are set to ‘0’.

See Section 7.6, "Reset Interface," on page 124 for details on reset.

11.3

Interrupts

11.3.1

SCI INTERRUPTS TO THE HOST

The functions described in the following sub-sections can generate a SCI event on the EC_SCI# pin. In the MEC1632,

an SCI event is considered the same as an ACPI wakeup or runtime event. The EC can also generate a SCI on the

EC_SCI# pin by setting the EC_SCI_ bit in the EC_SCI# Pin Interface on page 211.

11.3.2

INTERRUPTS TO THE EC

An Interrupt is generated to the EC on PM1_CTL2 bit of GIRQ13 Source Register by the Host writing to Power Man-

agement 1 Control Register 2 (PM1_CNTRL 2).

An Interrupt is generated to the EC on PM1_EN2 bit of GIRQ13 Source Register by the Host writing to Power Manage-

ment 1 Enable Register 2 (PM1_EN 2).

An Interrupt is generated to the EC on PM1_STS2 bit of GIRQ13 Source Register by the Host writing to Power Man-

agement 1 Status Register 2 (PM1_STS 2).

11.3.3

ACPI PM1 BLOCK SCI EVENT-GENERATING FUNCTIONS

11.3.3.1

Power Button with Override

The power button has a status and an enable bit in the PM1_BLK of registers to provide an SCI upon the button press.

The status bit is software Read/Writable by the EC; the enable bit is Read-only by the EC. It also has a status and enable

bit in the PM1_BLK of registers to indicate and control the power button override (fail-safe) event. These bits are not

required by ACPI. The power button override event status bit is software Read/Writable by the EC; the enable bit is soft-

ware read-only by the EC. The enable bit for the override event is located at bit 1 in the Power Management 1 Control

The PWRBTN_ bit is set by the Host to enable the generation of an SCI due to the power button event. The status bit

is set by the EC when it generates a power button event and is cleared by the Host writing a ‘1’ to this bit (writing a ‘0’

has no effect); it can also be cleared by the EC. If the enable bit is set, the EC will generate an SCI power management

event.

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