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MEC1632 Datasheet(PDF) 210 Page - Microchip Technology |
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MEC1632 Datasheet(HTML) 210 Page - Microchip Technology |
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210 / 636 page ![]() MEC1632 DS00001592B-page 210 2012-2018 Microchip Technology Inc. 11.4.5 POWER MANAGEMENT 1 CONTROL 1 (PM1_CNTRL 1) RESERVED Reserved bits return ‘0’ when read. 11.4.6 POWER MANAGEMENT 1 CONTROL 2 (PM1_CNTRL 2) Note 11-6 An interrupt (PM1_CTL2) is generated to the EC when the Host writes to this register. PWRBTNOR_EN This bit can be set or cleared by the Host, read by the EC. SLP_TYPx These bits can be set or cleared by the Host, read by the EC. SLP_EN Refer to Table 11-9, "SLP_EN Definition" TABLE 11-7: POWER MANAGEMENT 1 CONTROL REGISTER 1 (PM1_CNTRL 1) HOST OFFSET 04h 8-bit HOST SIZE EC OFFSET 104h EC SIZE POWER VTR 00h nSYS_RST DEFAULT BUS LPC SPB BYTE0 BIT D7D6D5 D4D3 D2 D1 D0 HOST TYPE R R R RRR RR EC TYPE R R R RRR RR BIT NAME Reserved TABLE 11-8: POWER MANAGEMENT 1 CONTROL REGISTER 2 (PM1_CNTRL 2) HOST OFFSET 5h 8-bit HOST SIZE EC OFFSET 105h EC SIZE POWER VTR 00h nSYS_RST DEFAULT BUS LPC SPB BYTE0 BIT D7 D6 D5 D4 D3 D2 D1 D0 HOST TYPE R R W R/W R/W R/W EC TYPE RR R/WC R R R BIT NAME Reserved SLP_ EN SLP_TYPx PWRBTNOR_ EN Reserved TABLE 11-9: SLP_EN DEFINITION Host / EC R/W Description Host Read Always reads 0 Write Writing a 0 has no effect, Writing a 1 sets this bit EC Read Reads the value of the bit Write Writing a 0 has no effect, Writing a 1 clears this bit |
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