MEC1632 datasheet(140/636 Pages) MICROCHIP

140 / 636 page

MEC1632

DS00001592B-page 140

 2012-2018 Microchip Technology Inc.

Note 7-50

Some EC accessible blocks have no Block Sleep Enable bit in the EC Blocks Sleep Enables Register

1. Table 7-48 describes these.

7.8.5

CLOCK REQUIRED STATUS REGISTERS

The Clock Required Status Registers indicates the core clock status per block as defined in Section 7.4.8, "Generic

Block Clocking Model," on page 105.Like the Block Sleep Enable Registers, there are two types of Clock Required

Status Registers: the LPC Blocks Clock Required Status Register and the EC Blocks Clock Required Status Registers.

When a bit in the Clock Required Status Registers is asserted (‘1’), the block is enabled and requires that the 20 MHz

Oscillator remain running as defined in "EC Power State Controls," on page 115.

When a bit in the Clock Required Status Registers is not asserted (‘0’), the block is either not enabled as defined in the

Generic Block Clocking Model, or has been commanded to sleep and no longer requires the 20 MHz Oscillator.

MCHP Reserved

–

Note:

MCHP Reserved Sleep Enable bits must

be set to ‘1’ to put the device into Heavy

and Deep Sleep States. See Table 7-14,

“EC Controlled Dynamic Power States,” on

page 112

Reserved

–

TABLE 7-48:

EC BLOCKS NOT CONTROLLED BY

EC Blocks Sleep Enables Registers

Block Name

Block Cross Reference

MCU Serial Debug Port

Section 41.0, "Trace FIFO Debug Port (TFDP)," on page 562

Master BC Link B

Section 39.0, "BC-Link Master," on page 547

Master BC Link A

Master BC Link D

Flash Interface

Section 14.0, "Embedded Flash Subsystem," on page 240

Section 16.0, "ARC 625D Embedded Controller," on page 280

Interrupt Aggregater

Section 17.0, "EC Interrupt Aggregator," on page 287 (see also Section 7.4.9.2.2,

"INTERRUPT AGGREGATOR CLOCK TREE," on page 109)

Week Alarm Timer

Section 22.0, "Week Alarm Interface," on page 370

GPIO

Section 24.0, "GPIO Interface," on page 388 (see also Section 7.4.9.2.3, "GPIO

CLOCK TREE," on page 109)

VCI

Section 34.0, "VBAT-Powered Control Interface," on page 499

VBAT_RAM

Section 35.0, "VBAT Powered RAM," on page 508

TABLE 7-47:

EC BLOCKS SLEEP ENABLES/CLOCK REQUIRED REGISTERS BIT NAMES

Bit Name

Block Name (

Note 7-50)

Block Cross Reference

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