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FS6407 Datasheet(PDF) 33 Page - NXP Semiconductors |
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FS6407 Datasheet(HTML) 33 Page - NXP Semiconductors |
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33 / 111 page  NXP Semiconductors 33 FS6407/FS6408 6.5 Fail-safe machine To fulfill safety critical applications, the FS6407/FS6408 integrates a dedicated fail-safe machine (FSM). The FSM is composed of three main sub-blocks: the voltage supervisor (VS), the Fail-safe state machine (FSSM), and the fail-safe output driver (FSO).The FSM is electrically independent from the rest of the circuitry, to avoid common cause failure. For this reason, the FSM has its own voltage regulators (analog and digital), dedicated bandgap, and its own oscillator. Three power supply pins (VSUP 1, 2, & 3) are used to overtake a pin lift issue. The internal voltage regulators are directly connected on VSUP (one bonding wire per pin is used). Additionally, the ground connection is redundant as well to avoid any loss of ground. All the voltages generated in the device are monitored by the voltage supervisor (under & overvoltage) owing to a dedicated internal voltage reference (different from the one used for the voltage regulators). The result is reported to the MCU through the SPI and delivered to the Fail-safe state machine (FSSM) for action, in case of a fault. All the safety relevant signals feed the FSSM, which handles the error handling and controls the fail-safe outputs. There are two fail-safe outputs: RSTB (asserted low to reset the MCU), and FS0B (asserted low to control any fail-safe circuitry). The Fail- safe machine is in charge of bringing and maintaining the application in a Fail-safe state. Four sub Fail-safe states are implemented to handle the different kinds of failures, and to give a chance for the system to come back to a normal state. 6.5.1 Fail-safe machine state diagram Figure 11. Detailed fail-safe state diagram From Anywhere PowerDown LBIST LBIST Done & VPRE>VPRE_UV SELECT pin config. detection 1ms elapsed & VCORE > VCORE_UV & VCCA > VCCA_UV & VAUX > VAUX_UV ABIST VPRE<VPRE_UV Release RSTb INIT FS NORMAL WD is RUNNING Assert RSTb ABIST Pass No external RST & No activate RST WD OK External RST Activate RST or WD Not OK Activate RST Activate RST External RST External RST No activate RST & RST delay expired - RSTb is asserted low - RSTb is asserted low - RSTb is asserted low - RSTb is released - Unlock SPI init registers - Start 256ms open window - RSTb is released - Start WD close/open window - RSTb delay running - RSTb is asserted low POR Fail-safe No POR Fail-safe Release FSOb RST_err_count = 0 & FS_OUT ok FS0B Low 2 > RST_error_count < 6 FS0b low & No activate RST & RST delay expired - FS0b is asserted low -FS0b is released Deep Fail Safe RST delay=8s OR Rst_error_count=6 IO_0 - VCAN/VCORE OFF - VAUX/VCCA OFF - Fail Safe OFF - FS0b = Low - RSTb = Low No FS0b RST delay=8s Ext. IC error (IO0:1 and/or IO4:5) Ext. IC error (IO0:1 and/or IO4:5) RSTb delay = 8s External RSTb = 8s |
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