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FS6407 Datasheet(PDF) 89 Page - NXP Semiconductors |
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FS6407 Datasheet(HTML) 89 Page - NXP Semiconductors |
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89 / 111 page  NXP Semiconductors 89 FS6407/FS6408 7.3.25 INIT SUPERVISOR3 Table 65. INIT SUPERVISOR3 register description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 1 100 01 1 P 0 Vcca_5 D Vaux_5 D 0 Secure _3 Secure _2 Secure _1 Secure _0 MISO SPI_G WU CAN_G Reserv ed IO_G Vpre_G Vcore_ G Vothers _G SPI_FS _err SPI_FS _CLK SPI_FS _req SPI_FS _Parity 0 Reserv ed Vcca_5 D Vaux_5 D Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 100 01 10 000 00 00 0 MISO SPI_G WU CAN_G Reserv ed IO_G Vpre_G Vcore_ G Vothers _G SPI_FS _err SPI_FS _CLK SPI_FS _req SPI_FS _Parity 0 Reserv ed Vcca_5 D Vaux_5 D Table 66. INIT SUPERVISOR3. Description and configuration of the bits (default value in bold) VCCA_5D Description Configure the VCCA undervoltage in degraded mode. Only valid for 5.0 V 0 Normal 5.0 V undervoltage detection threshold (VCCA_UV_5) 1 Degraded mode, i.e lower undervoltage detection threshold applied (VCCA_UV_D) Reset condition Power On Reset VAUX_5D Description Configure the VAUX undervoltage in degraded mode. Only valid for 5.0 V 0 Normal 5.0 V undervoltage detection threshold (VAUX_UV_5) 1 Degraded mode, i.e lower undervoltage detection threshold applied (VAUX_UV_5D) Reset condition Power On Reset Secure3:0 Description Secured bits based on write bits Secured_3 = NOT(bit5) Secured_2= NOT(bit4) Secured_1=bit7 Secured_0=bit6 SPI_FS_err Description Secured SPI communication check, concerns fail-safe logic only 0 No error 1 Error detected in the secured bits Reset condition Power On Reset SPI_FS_CLK Description SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both main and fail-safe logics. Other errors flagged by the SPI_CLK_ bit 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Power On Reset |
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