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FS6407 Datasheet(PDF) 70 Page - NXP Semiconductors |
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FS6407 Datasheet(HTML) 70 Page - NXP Semiconductors |
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70 / 111 page  70 NXP Semiconductors FS6407/FS6408 7.3.6 INIT INT WU_4_1:0 Description Wake-up configuration for IO_4 00 NO wake-up capability 01 Wake-up on rising edge only 10 Wake-up on falling edge only 11 Wake-up on any edge Reset condition Power On Reset WU_5_1:0 Description Wake-up configuration for IO_5 00 NO wake-up capability 01 Wake-up on rising edge only 10 Wake-up on falling edge only 11 Wake-up on any edge Reset condition Power On Reset INT_inh_IO_45 Description Inhibit the INT pulse for IO_4 & IO_5. IO_4 & IO_5 masked in IO_G. Avoid INT when used in FS 0 INT NOT masked 1INT masked Reset condition Power On Reset INT_inh_IO_23 Description Inhibit the INT pulse for IO_2 & IO_3. IO_2 & IO_3 masked in IO_G. Avoid INT when used in FS 0 INT NOT masked 1 INT masked Reset condition Power On Reset Table 27. INIT INT register description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 1 0 0 0 1 1 0 P INT_dur ation 0 INT_inh _all INT_inh _Vsns INT_inh _Vpre INT_inh _Vcore INT_inh _Vother s INT_inh _CAN MISO SPI_G WU CAN_G Reserved IO_G Vpre_G Vcore_ G Vothers _G INT_dur ation Reserve d INT_inh _all INT_inh _Vsns INT_inh _Vpre INT_inh _Vcore INT_inh _Vother s INT_inh _CAN Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserved IO_G Vpre_G Vcore_ G Vothers _G INT_dur ation Reserve d INT_inh _all INT_inh _Vsns INT_inh _Vpre INT_inh _Vcore INT_inh _Vother s INT_inh _CAN Table 26. INIT IO_WU2. Description and configuration of the bits (default value in bold) (continued) |
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