FS6407 datasheet(35/111 Pages) NXP

35 / 111 page

NXP Semiconductors

FS6407/FS6408

6.5.2.3

Watchdog in debug mode

When the device is in debug mode (entered via the DEBUG pin), the watchdog continues to operate, but does not affect the device

operation by asserting a reset or fail-safe pins. For the user, operation appears without the watchdog. If needed and to debug the

watchdog itself, the user can operate as in Normal mode and check LFSR values, the watchdog refresh counter, the watchdog error

counter, and reset counter. This allows the user to debug their software and ensure a good watchdog strategy in the application.

6.5.2.4

Wrong watchdog refresh handling

Error counters and strategy are implemented in the device to manage wrong watchdog refreshes from the MCU. According to consecutive

numbers of wrong watchdog refreshes, the device can decide to assert the RSTB only, or to go in deep Fail-safe mode where only a Power

On Reset or a transition on IO_O helps the system to recover.

6.5.2.5

Watchdog error counter

The watchdog error counter is implemented in the device to filter the incorrect watchdog refresh. Each time a watchdog failure occurs, the

device increments this counter by 2. The WD error counter is decremented by 1 each time the watchdog is properly refreshed. This

principle ensures that a cyclic “OK/NOK” behavior converges to a failure detection. To allow flexibility in the application, the maximum

value of this counter is configurable in the INIT_WD register, but only when device is in INIT FS mode.

Figure 14. Watchdog error counter configuration (INIT_WD register, bits WD_CNT_error_1:0)

WD refresh OK

WD refresh NOK

Watchdog Error Counter

WD_CNT_error = 4

WD refresh OK

WD refresh NOK

Watchdog Error Counter

WD_CNT_error = 6

WD refresh NOK

Watchdog Error Counter

WD_CNT_error = 2

FS6407 Datasheet(PDF) 35 Page - NXP Semiconductors