FS6407 datasheet(6/111 Pages) NXP

6 / 111 page

NXP Semiconductors

FS6407/FS6408

IO_4:5

D_IN

A_OUT

Can be used as digital input (load dump proof) with wake-up capability or as an output gate driver

Digital input: Pin status can be read through the SPI. Can be used to monitor error signals from another

IC for safety purposes.

Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a transition

Output gate driver: Can drive a logic level low-side NMOS transistor. Controlled by the SPI.

IO_0:1

A_IN

D_IN

Can be used as analog or digital input (load dump proof) with wake-up capability (selectable)

Analog input: Pin status can be read through the MUX output pin

Digital input: Pin status can be read through the SPI. Can be used to monitor error signals from another

IC for safety purposes

Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a transition

Rk: For safety purposes, IO_1 can also be used to monitor the middle point of a redundant resistor bridge

connected on VCORE (in parallel to the one used to set the Vcore voltage).

FS0B

D_OUT

Output of the safety block (active low). The pin is asserted low at start-up and when a fault condition is

detected. Open drain structure.

DEBUG

D_IN

Debug mode entry input

AGND

GROUND Analog ground connection

MUX_OUT

A_OUT

Multiplexed output to be connected to an MCU ADC input. Selection of the analog parameter is available

at MUX-OUT through the SPI.

IO_2:3

D_IN

Digital input pin with wake-up capability (logic level compatible)

Digital INPUT: Pin status can be read through the SPI. Can be used to monitor error signals from MCU for

safety purposes.

Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a transition.

TXD

D_IN

Transceiver input from the MCU which controls the state of the HSCAN bus. Internal pull-up to VDDIO.

Internal pull-up to VDDIO.

RXD

D_OUT

Receiver output which reports the state of the HSCAN bus to the MCU

RSTB

D_OUT

This output is asserted low when the safety block reports a failure. The main function is to reset the MCU.

Reset input voltage is also monitored in order to detect external reset and fault condition. Open drain

structure.

MISO

D_OUT

SPI bus. Master Input Slave Output

MOSI

D_IN

SPI bus. Master Output Slave Input

SCLK

D_IN

SPI Bus. Serial clock

NCS

D_IN

No Chip Select (Active low)

INTB

D_OUT

This output pin generates a low pulse when an Interrupt condition occurs. Pulse duration is configurable.

Internal pull-up to VDDIO.

VDDIO

A_IN

Input voltage for MISO output buffer. Allows voltage compatibility with MCU I/Os.

SELECT

D_IN

Hardware selection pin for VAUX and VCCA output voltages

FB_CORE

A_IN

VCORE voltage feedback. Input of the error amplifier.

COMP_CORE

A_IN

Compensation network. Output of the error amplifier.

VCORE_SNS

A_IN

VCORE output voltage sense

SW_CORE

A_IN

VCORE switching point

BOOT_CORE A_IN/OUT Bootstrap capacitor for VCORE internal NMOS gate drive

VPRE

A_OUT

VPRE output voltage

VAUX

A_OUT

VAUX output voltage. External PNP ballast transistor. Collector connection

VAUX_B

A_OUT

VAUX voltage regulator. External PNP ballast transistor. Base connection

VAUX_E

A_OUT

VAUX voltage regulator. External PNP ballast transistor. Emitter connection

VCCA_E

A_OUT

VCCA voltage regulator. External PNP ballast transistor. Emitter connection

VCCA_B

A_OUT

VCCA voltage regulator. External PNP ballast transistor. Base connection

Table 2. FS6407/FS6408 pin definition (continued)

Pin Number

Pin Name

Type

Definition

FS6407 Datasheet(PDF) 6 Page - NXP Semiconductors

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