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FS6407 Datasheet(PDF) 92 Page - NXP Semiconductors

Part # FS6407
Description  Power system basis chip with high speed can transceiver
PDF  111 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS6407 Datasheet(HTML) 92 Page - NXP Semiconductors

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NXP Semiconductors
FS6407/FS6408
7.3.27 Init FSSM2
Table 69. INIT FSSM2 register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
11
00
1
0
1
P
RSTb_
err_FS
IO_23_
FS
PS
0
Secure
_3
Secure
_2
Secure
_1
Secure
_0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G Vpre_G
Vcore_
G
Vothers
_G
SPI_FS
_err
SPI_FS
_CLK
SPI_FS
_req
SPI_FS
_Parity
RSTb_
err_FS
IO_23_
FS
PS
0
Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
1
0
010
10
00
000
00
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G Vpre_G
Vcore_
G
Vothers
_G
SPI_FS
_err
SPI_FS
_CLK
SPI_FS
_req
SPI_FS
_Parity
RSTb_
err_FS
IO_23_
FS
PS
0
Table 70. INIT FSSM2. Description and configuration of the bits (default value in bold)
IO_23_FS
Description
Configure the couple of IO_3:2 as safety inputs for FCCU monitoring
0
NOT SAFETY
1
SAFETY CRITICAL
Reset condition
Power On Reset
RSTb_err_FS
Description
Configure the values of the RSTb error counter
0
intermediate = 3; final = 6
1
intermediate = 1; final = 2
Reset condition
Power On Reset
PS
Description
Configure the FCCU polarity
0
Fccu_eaout_1:0 active HIGH
1
Fccu_eaout_1:0 active LOW
Reset condition
Power On Reset
Secure3:0
Description
Secured bits based on write bits
Secured_3 = NOT(bit5)
Secured_2 = NOT(bit4)
Secured_1 = bit7
Secured_0 = bit6
SPI_FS_err
Description
Secured SPI communication check, concerns fail-safe logic only
0No error
1
Error detected in the secured bits
Reset condition
Power On Reset



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