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FS6407 Datasheet(PDF) 83 Page - NXP Semiconductors

Part # FS6407
Description  Power system basis chip with high speed can transceiver
PDF  111 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS6407 Datasheet(HTML) 83 Page - NXP Semiconductors

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NXP Semiconductors
83
FS6407/FS6408
7.3.20 IO_OUT-AMUX
Table 54. VREG MODE. Description and configuration of the bits (default value in bold)
VCORE_EN
Description
VCORE control (Switch OFF NOT recommended if VCORE is SAFETY critical)
0
DISABLED
1
ENABLED
Reset condition
Power On Reset
VCCA_EN
Description
VCCA control (Switch OFF NOT recommended if VCCA is SAFETY critical)
0
DISABLED
1
ENABLED
Reset condition
Power On Reset
VAUX_EN
Description
VAUX control (Switch OFF NOT recommended if VAUX is SAFETY critical)
0
DISABLED
1
ENABLED
Reset condition
Power On Reset
VCAN_EN
Description
VCAN control
0
DISABLED
1
ENABLED
Reset condition
Power On Reset
Secure 3:0
Description
Secured bits based on write bits
Secured_3 = NOT(bit5)
Secured_2 = NOT(bit4)
Secured_1 = bit7
Secured_0 = bit6
Table 55. IO_OUT-AMUX register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
10101
11
P
IO_out
_4_EN
IO_out
_4
IO_out
_5_EN
IO_out
_5
0
Amux_
2
Amux_
1
Amux_
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G Vpre_G
Vcore_
G
Vothers
_G
IO_out
_4_EN
IO_oou
t_4
IO_out
_5_EN
IO_out
_5
Reserv
ed
Amux_
2
Amux_
1
Amux_
0
Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
00101
11000
00000
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G Vpre_G
Vcore_
G
Vothers
_G
IO_out
_4_EN
IO_out
_4
IO_out
_5_EN
IO_out
_5
Reserv
ed
Amux_
2
Amux_
1
Amux_
0



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