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FS6407 Datasheet(PDF) 87 Page - NXP Semiconductors |
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FS6407 Datasheet(HTML) 87 Page - NXP Semiconductors |
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87 / 111 page  NXP Semiconductors 87 FS6407/FS6408 7.3.24 INIT SUPERVISOR2 Secure3:0 Description Secured bits based on write bits Secured_3 = NOT(bit5) Secured_2 = NOT(bit4) Secured_1 = bit7 Secured_0 = bit6 SPI_FS_err Description Secured SPI communication check, concerns Fail-safe logic only 0 No error 1 Error detected in the secured bits Reset condition Power On Reset SPI_FS_CLK Description SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both main and fail-safe logics. Other errors flagged by the SPI_CLK_ bit 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Power On Reset SPI_FS_Req Description Invalid SPI access (Wrong Write or Read, Write to INIT registers in Normal mode, wrong address), concerns fail-safe logic only. 0 No error 1 SPI violation Reset condition Power On Reset SPI_FS_Parity Description SPI parity bit error detection, concerns fail-safe logic only 0 Parity bit OK 1 Parity bit ERROR Reset condition Power On Reset Table 63. INIT SUPERVISOR2 register description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 1100010 P Vaux_F S1 Vaux_F S_0 0 DIS_8s Secure _3 Secure _2 Secure _1 Secure _0 MISO SPI_G WU CAN_G Reserv ed IO_G Vpre_G Vcore_ G Vothers _G SPI_FS _err SPI_FS _CLK SPI_FS _req SPI_FS _Parity 0 DIS_8s Vaux_F S1 Vaux_F S_0 Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 01000100000 00000 MISO SPI_G WU CAN_G Reserv ed IO_G Vpre_G Vcore_ G Vothers _G SPI_FS _err SPI_FS _CLK SPI_FS _req SPI_FS _Parity 0 DIS_8s Vaux_F S1 Vaux_F S_0 Table 62. INIT SUPERVISOR1. Description and configuration of the bits (default value in bold) (continued) |
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