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RT600 Datasheet(PDF) 112 Page - NXP Semiconductors |
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RT600 Datasheet(HTML) 112 Page - NXP Semiconductors |
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112 / 171 page ![]() RT600 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors B.V. 2023. All rights reserved. Product data sheet Rev. 2.1 — 7 July 2023 112 of 173 NXP Semiconductors RT600 Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs 14.9 I2S-bus interface Excluding delays introduced by external device and PCB, the maximum supported bit rate for I2S master mode (transmit/receive) is 20 Mbit/s and the maximum supported bit rate for I2S slave mode (transmit/receive) is 20 Mbit/s. [1] Based on simulation; not tested in production. [2] Clock Divider register (DIV) = 0x0. [3] The Flexcomm Interface function clock frequency should not be above 140 MHz. See the data rates section in the I2S chapter (UM11147) to calculate clock and sample rates. Table 41. Dynamic characteristics: I2S-bus interface pins [1][3] Tamb = 0 C to 85 C; VDDIO_x = 1.71 V to 3.6 V.; VDDCORE = 1.13 V; CL = 10 pF balanced loading on all pins; Input slew = 1.0 ns, Full Output Drive mode for all pins, SLEW setting = standard mode for all pins; Parameters sampled at the 50% level of the rising or falling edge. Symbol Parameter Conditions Min Typ Max Unit Common to master and slave tWH pulse width HIGH on pins I2Sx_TX_SCK and I2Sx_RX_SCK 45% - 55% TCLK Period tWL pulse width LOW on pins I2Sx_TX_SCK and I2Sx_RX_SCK 45% - 55% TCLK Period Master tv(Q) data output valid time on pin I2Sx_TX_SDA [2] 0 - 20 ns on pin I2Sx_WS 0 - 20 ns tsu(D) data input set-up time on pin I2Sx_RX_SDA [2] 8 - - ns th(D) data input hold time on pin I2Sx_RX_SDA [2] 0 - - ns Slave tv(Q) data output valid time on pin I2Sx_TX_SDA [2] 0 - 20 ns tsu(D) data input set-up time on pin I2Sx_RX_SDA [2] 8 - - ns on pin I2Sx_WS 8 - - ns th(D) data input hold time on pin I2Sx_RX_SDA [2] 0 - - ns on pin I2Sx_WS 0 - - ns |
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