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ATMEGA640 Datasheet(PDF) 164 Page - ATMEL Corporation |
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ATMEGA640 Datasheet(HTML) 164 Page - ATMEL Corporation |
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164 / 449 page ![]() 164 ATmega640/1280/1281/2560/2561 2549K–AVR–01/07 TCCR1C – Timer/Counter 1 Control Register C TCCR3C – Timer/Counter 3 Control Register C TCCR4C – Timer/Counter 4 Control Register C TCCR5C – Timer/Counter 5 Control Register C • Bit 7 – FOCnA: Force Output Compare for Channel A • Bit 6 – FOCnB: Force Output Compare for Channel B • Bit 5 – FOCnC: Force Output Compare for Channel C The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB/FOCnB bits are always read as zero. • Bit 4:0 – Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to zero when TCCRnC is written. Bit 765 4 3 210 (0x82) FOC1A FOC1B FOC1C – – – – – TCCR1C Read/Write WW W RR R R R Initial Value 0 0 0 0 0 0 0 0 Bit 765 4 3 210 (0x92) FOC3A FOC3B FOC3C – – – – – TCCR3C Read/Write WW W RR R R R Initial Value 0 0 0 0 0 0 0 0 Bit 765 4 3 210 (0xA2) FOC4A FOC4B FOC4C – – – – – TCCR4C Read/Write WW W RR R R R Initial Value 0 0 0 0 0 0 0 0 Bit 765 4 3 210 (0x122) FOC5A FOC5B FOC3C – – – – – TCCR5C Read/Write WW W RR R R R Initial Value 0 0 0 0 0 0 0 0 |
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