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ATMEGA640 Datasheet(PDF) 165 Page - ATMEL Corporation |
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ATMEGA640 Datasheet(HTML) 165 Page - ATMEL Corporation |
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165 / 449 page  165 ATmega640/1280/1281/2560/2561 2549K–AVR–01/07 TCNT1H and TCNT1L – Timer/Counter 1 TCNT3H and TCNT3L – Timer/Counter 3 TCNT4H and TCNT4L – Timer/Counter 4 TCNT5H and TCNT5L – Timer/Counter 5 The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit tempo- rary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 139. Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a compare match between TCNTn and one of the OCRnx Registers. Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock for all compare units. Bit 7654 321 0 (0x85) TCNT1[15:8] TCNT1H (0x84) TCNT1[7:0] TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 000 0 Bit 7654 321 0 (0x95) TCNT3[15:8] TCNT3H (0x94) TCNT3[7:0] TCNT3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 000 0 Bit 7654 321 0 (0xA5) TCNT4[15:8] TCNT4H (0xA4) TCNT4[7:0] TCNT4L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 000 0 Bit 7654 321 0 (0x125) TCNT5[15:8] TCNT5H (0x124) TCNT5[7:0] TCNT5L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 000 0 |
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