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AD9898

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Special Vertical Timing (SPAT)

The AD9898 provides additional special vertical timing (SPAT)

generation, which is output in the same line as the VSG pulse.

The SPAT timing allows for configuring a second vertical out-

put pulse in the VSG line. Tables XIX and XX list the registers

used to generate the SPAT timing.

Figures 35 and 36 show how the SPAT timing can be either an

AND case or an OR case, depending on the value set in the

SPATLOGIC register. As these figures show, the internal SPAT

timing for the AND case will start High and then go Low at the

first VxSPAT_TOG1 position. In the OR case, the internal

Table XIX. HD and VD Registers

Bit

Reference

Range

Name

Width

Counter

Pixels

Description

SPAT_EN

Control (Addr 0x0A)

SPAT Enable Control

(0 = SPAT Disabled, 1 = SPAT Enabled)

SPATLOGIC

Control (Addr 0x0A)

SPAT Logic Setting

V1SPAT_TOG1

Mode_Reg(5)

0–8192

Polarity Change Position Start for V1 SPAT

V1SPAT_TOG2

Mode_Reg(5)

0–8192

Polarity Change Position End for V1 SPAT

V2SPAT_TOG1

Mode_Reg(6)

0–8192

Polarity Change Position Start for V2 SPAT

V2SPAT_TOG2

Mode_Reg(6)

0–8192

Polarity Change Position End for V2 SPAT

V3SPAT_TOG1

Mode_Reg(6 and 7)

0–8192

Polarity Change Position Start for V3 SPAT

V3SPAT_TOG2

Mode_Reg(7)

0–8192

Polarity Change Position End for V3 SPAT

V4SPAT_TOG1

Mode_Reg(7)

0–8192

Polarity Change Position Start for V4 SPAT

V4SPAT_TOG2

Mode_Reg(7 and 8)

0–8192

Polarity Change Position End for V4 SPAT

1. THE VxSPAT_TOG1 AND VxSPAT_TOG2 REGISTERS REFERENCE THE 13-BIT ST COUNTER.

2. THE INTERNAL SPAT TIMING IS APPLIED IN THE SAME LINE AS THE VSGx PULSE.

PROGRAMMABLE CLOCK POSITIONS

1. VxSPAT_TOG1 (PROGRAMMABLE AT MODE_REGs).

2. VxSPAT_TOG2 (PROGRAMMABLE AT MODE_REGs).

13-BIT

ST COUNTER

(FIXED)

INTERNAL V2

WITHOUT

SPAT APPLIED

INTERNAL SPAT

TIMING FOR V2 WITH

SPATLOGIC = 1

V2 OUTPUT WITH

SPAT APPLIED

VSGx

Figure 35. SPAT Example Applied to V2 with SPATLOGIC = xx1x

SPAT timing will initially start Low and then toggle High at the

first VxSPAT_TOG1 position. This provides the ability to

output the second vertical pulse when the internal Vx pulse is

in both High and Low states.

Table XX. SPATLOGIC Register (Addr 0x0A)

SPATLOGIC [3:0]

Description

0 = OR, 1 = AND

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