AD9898 datasheet(5/52 Pages) AD

Part #	AD9898

Description	CCD Signal Processor with Precision Timing??Generator

PDF	52 Pages

Scroll/Zoom	100%

Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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5 / 52 page

REV. 0

AD9898

–5–

TIMING SPECIFICATIONS (C

L = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 20 MHz, unless otherwise noted.)

Parameter

Symbol

Min

Typ

Max

Unit

MASTER CLOCK, CLI

CLI Clock Period

tCONV

CLI High/Low Pulsewidth

Delay from CLI Rising Edge to Internal Pixel Position 0

tCLIDLY

6ns

AFE CLAMP PULSES

CLPOB Pulsewidth

Pixels

AFE SAMPLE LOCATION

* (See Figure 13)

SHP Sample Edge to SHD Sample Edge

tS1

Pixels

DATA OUTPUTS (See Figure 15)

Output Delay from DCLK Rising Edge

tOD

9ns

Pipeline Delay from SHP/SHD Sampling

Cycles

SERIAL INTERFACE (See Figures 7 and 8)

Maximum SCK Frequency

fSCLK

MHz

SL to SCK Setup Time

tLS

SCK to SL Hold Time

tLH

SDATA Valid to SCK Rising Edge Setup

tDS

SCK Falling Edge to SDATA Valid Hold

tDH

SCK Falling Edge to SDATA Valid Read

tDV

*Parameter is programmable.

Specifications subject to change without notice.

AD9898 Datasheet(PDF) 5 Page - Analog Devices

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