AD9898 datasheet(17/52 Pages) AD

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AD9898

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SERIAL INTERFACE TIMING

All of the internal registers of the AD9898 are accessed through a

3-wire serial interface. The interface consists of a clock (SCK),

serial load (SL), and serial data (SDATA).

The AD9898 has three different register types that are config-

ured by the 3-wire serial interface. They are control registers,

system registers, and mode registers and are described in Table VI.

Table VI. Type of Serial Interface Registers

Address

No. of Registers

Control

0x00 through

There is a 24-bit register at each

0xD6

address. Not all addresses are

used. See Table I.

System

0x14

Seventeen 32-bit system registers

at Address 0x14. See Table II.

Mode_A

0x15

Eight 32-bit Mode_A registers at

Address 0x15. See Table III.

Mode_B

0x16

Eight 32-bit Mode_B registers at

Address 0x16. See Table IV.

Control Register Serial Interface

The control register 3-wire interface timing requirements are

shown in Figure 7. Control data must be written into the device

one address at a time due to the noncontiguous address spacing

for the control registers. This requires eight bits of address data

followed by 24 bits of configuration data between each active

low period of SL for each address. The SL signal must be kept

high for at least one full SCK cycle between successive writes to

control registers.

System Register Serial Interface

There are seventeen 32-bit system registers that get accessed

sequentially at Address 0x14 beginning with Sys_Reg[0]. When

writing to the system registers, SDATA contains the 8-bit address

of 0x14, followed by Number Writes N[23:0], followed by the

Sys_Reg[31:0] data as shown in Figure 8. The system register

map is listed in Table II.

There are two options available when writing to the system

registers. The choice is automatically determined by the value of

the Number Writes N[23:0] word. If Number Writes N[23:0] =

0x000000, the device gets put into a mode where it expects all

17 Sys_Reg[31:0] data-words to be clocked in before SL is

asserted high. If the Number Writes N[23:0] is decoded as

some number N other than 0x000000, the device expects N

number of registers to be programmed where N is equal to the

value of Number Writes N[23:0]. For example, if Number

Writes N[23:0] = 0x000004, the device would expect data to be

provided for Sys_Reg[3:0]. In all cases, the system registers

would be written to begin with Sys_Reg[0], no matter what the

value of Number Writes N[23:0] is. Note that SL can be brought

high or low during access to system registers, as shown in Figure 8.

Mode_A and Mode_B Register Serial Interface

There are eight 32-bit Mode_A and eight 32-bit Mode_B regis-

ters that get accessed sequentially at Address 0x15 and Address

0x16, respectively. The Mode_A and Mode_B registers get

written to exactly as the system registers are. (See the descrip-

tion above.) The mode registers are listed in Tables III and IV.

Changing operation between Mode_A and Mode_B is done by

setting the 1-bit MODE register (Addr 0x0A). The desired

Mode_A (Addr 0x15) or Mode_B (Addr 0x16) data must be

programmed into the Mode_A or Mode_B registers before

changing the MODE bit.

SDATA

SCK

D22

D21

1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.

2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.

3. THIS TIMING PATTERN MUST BE WRITTEN FOR EACH REGISTER WRITE WITH SL REMAINING HIGH FOR AT

LEAST ONE FULL SCK PERIOD BEFORE ASSERTING SL LOW AGAIN FOR THE NEXT REGISTER WRITE.

D23

....

tDS

tDH

tLH

tLS

Figure 7. 3-Wire Serial Interface Timing for Control Registers

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