AD9898 datasheet(44/52 Pages) AD

44 / 52 page

REV. 0

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AD9898

STROBE Control

The AD9898 provides a STROBE output pulse that can be used

to trigger the camera flash circuit. STROBE operation is set by

only one register, as described in Table XXV. The STROBE

output is held Low when STROBE_EN (Addr 0x0B) is set to

0 and enabled when set to 1. Providing STROBE_EN = 1, the

STROBE output pulse will be asserted High on the rising edge of

the last SUBCK pulse in the field, as shown in Figure 48.

Figure 48 also shows the STROBE pulse asserted Low again on

the rising edge of VSG.

SLAVE AND MASTER MODE OPERATION

The AD9898 can be operated in either slave mode or master

mode. It defaults to the slave mode operation at power-up. The

1. STROBE OUTPUT ASSERTED HIGH ON RISING EDGE OF LAST SUBCK PULSE.

2. STROBE OUTPUT ASSERTED LOW ON NEGATIVE EDGE OF VSG PULSE.

SUBCK

STROBE

VSG1–

VSG2

tEXP

SET STROBE_EN (ADDR 0x0B) = 1

Figure 48. STROBE Output Timing

INTERNAL 12-BIT H-GRAY CODE COUNTER IS RESET 7 CLOCK CYCLES AFTER THE HD FALLING EDGE.

CLI

H-GRAY CODE

COUNTER

(PIXEL COUNTER)

XXXXX

4567

H-COUNTER

RESET

H-COUNTER

RESET

3ns MIN

Figure 49. External VD/HD and Internal 12-Bit H-Gray Code Counter Synchronization, SLAVE Mode

SLAVE_MODE register (Addr 0xD6) can be used to configure

the AD9898 into master mode by setting SLAVE_MODE = 0.

Slave Mode Operation

While operating in slave mode, VD, HD, and VGATE are pro-

vided externally from the image processor. VGATE is input

active high on Pin 45. Unlike master mode operation, there is a

7 CLI clock cycle delay from the falling edge of HD to when the

12-bit gray code H counter is reset to zero (see Figure 49).

Master Mode Operation

While operating in master mode, VD and HD are outputs and

the SYNC/VGATE pin is configured as an external SYNC input.

Master mode is selected by setting register SLAVE_MODE

(Addr 0xD6) = 0.

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