AD9898 datasheet(19/52 Pages) AD

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AD9898

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ANALOG FRONT END (AFE) DESCRIPTION AND

OPERATION

The AD9898 AFE signal processing chain is shown in Figure 10.

Each processing step is essential to achieving a high quality image

from the raw CCD pixel data. Registers for the AD9898 AFE

section are listed in Table VII.

DC Restore

To reduce the large dc offset of the CCD output signal, a dc

restore circuit is used with an external 0.1

µF series coupling

capacitor. This restores the dc level of the CCD signal to approxi-

mately 1.5 V, which is compatible with the 3 V analog supply of

the AD9898.

Correlated Double Sampler

To extract the video information and reject low frequency noise,

the CDS circuit samples each CCD pixel twice. The timing

shown in Figure 12 illustrates how the two internally generated

CDS clocks, SHP and SHD, are used to sample the reference

level and the data level of the CCD signal, respectively. The

placement of the SHP and SHD sampling edges is determined

by the setting of the SHPLOC (Addr 0x02) and SHDLOC

(Addr 0x02) registers. Placement of these two clock edges is criti-

cal to achieving the best performance from the CCD.

Table VII. AFE Registers

Bit

Name

Width Register Type

Description

VGAGAIN

Control (Addr 0x0E) VGA Gain

REFBLACK 6

Control (Addr 0x04)

Blk Clamp Level

AFESTBY

Control (Addr 0x05)

AFE Standby

6dB TO 40dB

DIGITAL

FILTER

CLPOB

DC RESTORE

OPTICAL BLACK

CLAMP

ADC

VGA

8-BIT

DAC

CLAMP LEVEL

VGA GAIN

CDS

INTERNAL

VREF

2V FULL

SCALE

PRECISION

TIMING

GENERATION

SHP

SHD

1.5V

REFT

REFB

DOUT

PHASE

V-H

TIMING

GENERATION

SHP

SHD

DOUT

PHASE

CLPOB

1.0V

2.0V

DOUT

1.0 F

CCDIN

AD9898

0.1 F

OUTPUT

DATA

LATCH

Figure 10. AFE Block Diagram

PRECISION TIMING HIGH SPEED TIMING GENERATION

The AD9898 generates flexible high speed timing signals using

the Precision Timing core. This core is the foundation for gen-

erating the timing used for both the CCD and the AFE signals,

including the reset gate RG, the horizontal drivers H1–H2, and

the CDS sample clocks. By providing precise control over the

horizontal CCD readout and the AFE correlated double sampling,

the unique architecture of the AD9898 makes optimizing image

quality a routine task for a system designer.

Timing Resolution

The Precision Timing core uses a 1

× master clock input (CLI)

as a reference. This clock should be the same as the CCD pixel

clock frequency. Figure 11 illustrates how the internal timing

core divides the master clock period into 48 steps or edge posi-

tions. Using a 20 MHz CLI frequency for the AD9898, the

edge resolution of the Precision Timing core is 1 ns. A 40 MHz

CLI frequency can be applied where the AD9898 will inter-

nally divide the CLI frequency by two. Division by one-third

and one-fourth is also provided. CLI frequency division is con-

trolled using the CLKDIV (Addr 0xD5) register.

High Speed Clock Programmability

Figure 13 shows how the high speed clocks RG, H1–H2, SHP,

and SHD are generated. The RG pulse has a fixed rising edge

and a programmable falling edge. The horizontal clock H1

has a programmable rising and a fixed falling edge occurring at

H1POSLOC + 24 steps. The H2 clock is always the inverse of

H1. Table VIII summarizes the high speed timing registers and

the parameters for the high speed clocks. Each register is six bits

wide with the 2 MSB used to select the quadrant region as

outlined in Table VIII. Figure 13 shows the range and de-

fault locations of the high speed clock signals.

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