AD9898 datasheet(16/52 Pages) AD

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AD9898

SYSTEM OVERVIEW

Figure 5 shows the typical system block diagram for the AD9898.

The CCD output is processed by the AD9898’s AFE circuitry,

which consists of a CDS, VGA, black level clamp, and A/D

converter. The digitized pixel information is sent to the digital

image processor chip, which performs the postprocessing and

compression. To operate the CCD, all CCD timing parameters

are programmed into the AD9898 from the system micropro-

cessor, through the 3-wire serial interface. From the system

master clock, CLI, provided by the image processor or external

crystal, the AD9898 generates all the CCD’s horizontal and

vertical clocks and all internal AFE clocks. External synchroni-

zation is provided by a SYNC pulse from the microprocessor,

which will reset internal counters and resynchronize the VD and

HD outputs.

V-DRIVER

CCD

AD9898

DIGITAL

IMAGE

PROCESSING

ASIC

CLI

VGATE

HD, VD

DOUT[9:0]

DCLK1

MSHUT

STROBE

H1, H2, RG, VSUB

CCDIN

V1–V4, VSG1, VSG2, SUBCK

SERIAL

INTERFACE

SYNC

OUTCONT

Figure 5. Typical System Block Diagram, Master Mode

The AD9898 powers up in slave mode, in which the VD and

HD are provided externally from the image processor. In this

mode, all AD9898 timing will be synchronized with VD and

HD. The H-drivers for H1–H2 and RG are included in the

AD9898, allowing these clocks to be directly connected to the

CCD. H-drive voltage of up to 3.6 V is supported. An external

V-driver is required for the vertical transfer clocks, the sensor

gate pulses, and the substrate clock. The AD9898 also includes

programmable MSHUT and STROBE outputs, which may be

used to trigger mechanical shutter and strobe (flash) circuitry.

Figure 6 shows the horizontal and vertical counter dimensions

for the AD9898. All internal horizontal and vertical clocking is

programmed using these dimensions and is used to specify line

and pixel locations.

12-BIT HORIZONTALCOUNTER = 4096 PIXELS MAX

MAXIMUM FIELD DIMENSIONS

Figure 6. Horizontal and Vertical Counters

CLI INPUT CLOCK DIVIDER

The AD9898 provides the capability of dividing the CLI input

clock using register CLKDIV (Addr 0xD5). The following

procedure must be followed to reset the AFE and digital circuits

when CLKDIV is reprogrammed back to 0 from CLKDIV = 1,

2, or 3. The DCLK1 output will become unstable if this proce-

dure is not followed:

Step 1: CLKDIV = 1, 2, or 3 (CLI divided by setting value)

Step 2: CLKDIV = 0 (CLI reprogrammed for no division)

Step 3: DIGSTBY = AFESTBY = 0

Step 4: DIGSTBY = AFESTBY = 1

GRAY CODE REGISTERS

Table V lists the AD9898 registers requiring gray code values.

Below is an example of applying a gray code number for

HDLEN using a line length of 1560 pixels:

HDLEN = (1560 – 4) = 155610

(See Table XI note about HDLEN.)

155610 = 0x51E

The gray code value of 0x51E would be programmed in the

12-bit HDLEN register.

Table V. Gray Code Registers

HDLEN

System_Reg(12)

CLPTOG1

System_Reg(15)

CLPTOG2

System_Reg(15 and 16)

HDLASTLEN

Mode_Reg(1)

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