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AD9898 Datasheet(PDF) 46 Page - Analog Devices |
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AD9898 Datasheet(HTML) 46 Page - Analog Devices |
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46 / 52 page ![]() REV. 0 –46– AD9898 1 2 45 6 7 ODD FIELD EVEN FIELD 1H tDELAY3 tSETTLING4 tPWR H1, V1, V2, V3, VSG1, VSG2, VSUB, SUBCK, FD VDD (INPUT) VD (OUTPUT) DIGITAL OUTPUTS CLI (INPUT) HD (OUTPUT) SERIAL WRITES OUTCONT1 (INTERNAL SIGNAL) NOTES 1OUTCONT IS AN INTERNAL SIGNAL CONTROLLED USING REGISTER OUTCONT_REG (ADDR 0x05). 2DCLK2 WILL BE OUTPUT ON FD/DLCK2, PIN 16, PROVIDING REGISTER DCLK2SEL (ADDR 0xD5) = 1. 3IT TAKES 11 CLI CLOCKS FROM WHEN OUTCONT GOES HIGH UNTIL VD, HD, AND DIGITAL OUTPUT DATA IS VALID. 4THERE IS 500 s SETTLING TIME FROM WHEN THE DIGSTBY REGISTER IS SET TO WHEN THE DLCK1 IS STABLE. 1V H2, RG, MSHUT, STROBE DCLK1 (OUTPUT) DCLK22 (OUTPUT) ODD FIELD 89 10 Figure 51. Recommended Power-Up Sequence and Synchronization, Master Mode POWER-UP Recommended Power-Up Sequence for Master Mode When the AD9898 is powered up, the following sequence is recommended. (Refer to Figure 51 for each step.) 1. Turn on power supplies for AD9898. 2. Apply the CLI master clock input. CLI will be output on DCLK2 (Pin 16) at this time. 3. Reset the internal AD9898 registers. Write a 0x000000 to the SW_RESET register (Addr 0x00). This will set all internal register values to their default values. (This step is optional because an internal power-on reset circuit is applied at power-up.) 4. Program the DIGSTBY and AFESTBY registers (Addr 0x05) = 1, and program all other necessary control registers. 5. Program system registers (Addr 0x14). 6. Program Mode_A registers (Addr 0x15). 7. Program Mode_B registers (Addr 0x16). 8. Program OUTCONT_REG register (addr 0x05) = 1. (The internal OUTCONT signal will be asserted high at this time and will enable the digital outputs.) 9. Program control register MODE (Addr 0x0A) = 0. This selects Mode_A operation. (This step is optional because the AD9898 defaults to Mode_A at initial power-up.) 10. Program control register MODE (Addr 0x0A) = 1. This selects Mode_B operation. Complete this write at least four CLI cycles before start of the next field. |
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