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XRT79L71IB Datasheet(PDF) 89 Page - Exar Corporation |
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XRT79L71IB Datasheet(HTML) 89 Page - Exar Corporation |
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89 / 434 page ![]() XRT79L71 80 REV. 1.0.0 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION 5 Change of AIS Defect Condition Interrupt Status RUR Change in AIS Defect Condition Interrupt Status: This RESET-upon-READ register indicates whether or not the Change in AIS Defect Condition Interrupt has occurred since the last read of this register as depicted below. 0 - The Change in AIS Defect Condition Interrupt has not occurred since the last read of this register. 1 - The Change in AIS Defect Condition Interrupt has occurred since the last read of this register. 4 Change of DS3 Idle Condition Interrupt Status RUR Change in DS3 Idle Condition Interrupt Status: This RESET-upon-READ register indicates whether or not the Change in DS3 Idle Condition interrupt has occurred since the last read of this register. 0 - The Change in DS3 Idle Condition Interrupt has not occurred since the last read of this register. 1 - The Change in DS3 Idle Condition Interrupt has occurred since the last read of this register. 3 Change of FERF/RDI Defect Condition Inter- rupt Status RUR Change in FERF/RDI Defect Condition Interrupt Status: This RESET-upon-READ register indicates whether or not the Change in FERF/RDI Defect Condition Interrupt has occurred since the last read of this register. 0 - The Change in FERF/RDI Defect Condition Interrupt has not occurred since the last read of this register. 1 - The Change in FERF/RDI Defect Condition Interrupt has occurred since the last read of this register. 2 Change of AIC State Interrupt Status RUR Change in AIC State Interrupt Status: This RESET-upon-READ register bit indicates whether or not the Change in AIC State interrupt has occurred since the last read of this register. 0 - The Change in AIC State Interrupt has not occurred since the last read of this register. 1 - The Change in AIC State Interrupt has occurred since the last read of this register. 1 Change of OOF Defect Condition Interrupt Status RUR Change in OOF Defect Condition Interrupt Status: This RESET-upon-READ register indicates whether or not the Change in OOF Defect Condition Interrupt has occurred since the last read of this register. 0 - The Change in OOF Defect Condition Interrupt has not occurred since the last read of this register. 1 - The Change in OOF Defect Condition Interrupt has occurred since the last read of this register. 0 Detection of P-Bit Error Interrupt Status RUR Detection of P-Bit Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the Detection of CP-Bit Error Interrupt has occurred since the last read of this register. 0 - The Detection of CP-Bit Error Interrupt has not occurred since the last read of this register. 1 - The Detection of CP-Bit Error Interrupt has occurred since the last read of this register. BIT NUMBER NAME TYPE DESCRIPTION |
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