AP72202

Document number: DS46304 Rev. 1 - 2

7 of 30

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May 2024

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AP72202

Electrical Characteristics (continued)

I2C

– Compatible Interface Timing (Standard, Fast, and Fast Mode Plus) (Note 8)

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

fSCL

Clock Frequency

—

—

—

—

MHz

tSU;STA

Setup Time (Repeated) Start

Condition

SCL rising edge to SDA

falling edge; Both crossing

High threshold

0.26

—

—

μs

tHD;STA

Hold Time (Repeated) Start

Condition

From SDA falling edge

crossing Low threshold to

SCL falling edge crossing

High threshold

0.26

—

—

μs

tLOW

SCL Low Period

Time measured during the

Low voltage threshold

0.5

—

—

μs

tHIGH

SCL High Period

Time measured during the

High voltage threshold

0.26

—

—

μs

tHD;DAT

Input Data Hold Time

From SCL falling edge

crossing Low threshold to

SDA entering the Low-High

window

0

—

—

μs

tSU;DAT

Input Data Setup Time

From SDA exiting the Low-

High window to SCL rising

edge crossing Low threshold

50

—

—

ns

tSU;STO

Setup Time for Stop Condition

From SCL rising edge

crossing High threshold to

SDA rising edge crossing Low

threshold

0.26

—

—

μs

tBUF

Bus-Free Time Between Stop and

Start

From SDA crossing High

threshold during STOP

condition to SDA crossing

High threshold for the

following START condition

0.5

—

—

μs

tSP

Maximum Pulse Width of Spike That

Must be Suppressed by the Input

Filter

Any pulse width narrower

than the maximum

specification is suppressed

—

50

—

ns

CB

Capacitive Load for Each Bus Line

Total on-chip and off-chip

capacitance

—

—

550

pF

Note:

8. All min/max parameters compliance to the datasheet limits are assured by one or more methods: production test, characterization, and/or design.