AP72202

Document number: DS46304 Rev. 1 - 2

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AP72202

Application Information (continued)

Serial Interface

The I2C compatible 2-wire serial interface is used for regulator on/off control, setting output voltages, and other functions. See the Register Map

section for details. The I2C interface is an open-drain serial bus that consists of a bidirectional serial data line (SDA) and a serial clock line (SCL).

Pull

up resistors of 500Ω each or greater must be added from VIO to SDA and VIO to SCL. Optional 24Ω resistors in series with SDA and SCL help

to protect the device inputs from high voltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot on bus lines.

System Configuration

Figure 3. Functional Logic Diagram for Communications Controller

The I2C bus is a multi-master bus. The maximum number of devices that can attach to the bus is limited by bus capacitance. The figure above shows

an example of a typical I2C system. A device on the I2C bus that sends data to the bus is called a transmitter. A device that receives data from the

bus is called a receiver. The device that initiates a data transfer and generates the SCL clock signal to control the data transfer is the master. Any

device on the bus that can be addressed by the master is considered a slave. When the AP72202 I2C compatible interface is operating, it is a slave

on I2C bus.

Bit Transfer

One data bit is transferred for each SCL clock cycle. The data on SDA must remain stable during the high portion of SCL clock pulse. Changes in

SDA while SCL is high are control signals (START and STOP conditions).

Figure 4. I2C Bit Transfer

START and STOP Conditions

When the I2C serial interface is inactive, SDA and SCL are pulled high. A master device initiates communication by issuing a START (S) condition.

A START condition is a high-to-low transition on SDA while SCL is high. A STOP (P) condition is a low-to-high transition on SDA while SCL is high.

A START condition from the master signals the AP72202 that a transmission is about to begin. The master terminates transmission and frees the

bus by issuing a STOP condition. To issue a series of commands to the slave, the master may issue REPEATED START (Sr) conditions instead of

a STOP condition in order to maintain control of the bus. In general, a REPEATED START condition is functionally equivalent to a regular START

condition. The AP72202 will listen for its address after a START condition is detected. If its address is not detected, it will stay idle until the next

START condition is detected.

Figure 5. Start and Stop Conditions

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