AP72202

Document number: DS46304 Rev. 1 - 2

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May 2024

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AP72202

Application Information (continued)

Acknowledge

Both I2C bus master and AP72202 (slave) generate ACKNOWLEDGE (ACK) bits when receiving data. The ACK bit is the last bit of each nine bit

data packet. To generate an ACK bit, the receiving device must pull SDA low before the rising edge of the ACK-related clock pulse (ninth SCL pulse)

and keep it low during the high period of the clock pulse. To generate a NOT ACKNOWLEDGE (nACK), the receiving device allows SDA to be pulled

high before the rising edge of the ACK-related clock pulse and leaves it high during the high period of the clock pulse. Monitoring the ACK bits allows

for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In

the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time.

Slave Address

The I2C slave address of the AP72202 is shown in table below:

Slave Address (7 Bit)

Slave Address (Write)

Slave Address (Read)

100 0011

0x86 (1000 0110)

0x87 (1000 0111)

Figure 6. Slave Address Byte Example

Clock Stretching

In general, the clock signal generation for the I2C bus is the responsibility of the master device. I2C specification allows slow slave devices to alter

the clock signal by holding down the clock line. The process in which a slave device holds down the clock line is typically called clock stretching.

The AP72202 does not use any form of clock stretching to hold down the clock line.

General Call Address

The AP72202 does not implement the I2C specification called general call address. If the AP72202 sees a general call address (00000000b), it does

not issue an ACKNOWLEDGE.

Communication Speed

The AP72202 provides I2C 3.0-compatible serial interface.

•

I2C revision 3-compatible serial communications channel

• 0 to 100kHz (Standard-mode)

• 0 to 400kHz (Fast-mode)

• 0 to 1MHz (Fast-mode Plus)

• 0 to 3.4MHz (High-Speed mode)

• Does not utilize I2C clock stretching

Operating in Standard-mode, Fast-mode, or Fast-mode Plus does not require any special protocols. The main consideration when changing the bus

speed through this range is the combination of the bus capacitance and pullup resistors. Higher time constants created by the bus capacitance and

pullup resistance (C x R) slow the bus operation. Therefore, when increasing bus speeds, the pullup resistance must be decreased to maintain a

reasonable time constant. Refer to the Pullup Resistor Sizing section of I2C revision 3.0 specification for detailed guidance on the pullup resistor

selection. In general, for bus capacitances of 200pF, a 100kHz bus needs pullup resistors of 5.6k

, a 400kHz bus needs about a 1.5kΩ pullup

resistors, and a 1MHz bus needs 680

Ω pullup resistors. Note that the pullup resistor is dissipating power when the open-drain bus is low. Lower

values of the pullup resistors result in higher power dissipation (V2/R).

Operating in High-Speed (HS) mode requires some special considerations. For the full list of considerations, refer to the I2C 3.0 specification. The

major considerations with respect to the AP72202 are:

•

The I2C bus master uses current source pullups to shorten the signal rise times.

•

The I2C slave must use a different set of input filters on its SDA and SCL lines to accommodate for the higher bus speed.

•

The communication protocols need to utilize the High-Speed master code.

At power-up or after each STOP condition, the AP72202 inputs filters are set for Standard-mode, Fast-mode, or Fast-mode Plus (i.e. 0 to 1MHz).

Use the High-Speed master code protocols that are described in Communication Protocols section to switch the input filters for High-Speed mode.

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