AP72202

Document number: DS46304 Rev. 1 - 2

18 of 30

www.diodes.com

May 2024

© 2024 Copyright Diodes Incorporated. All Rights Reserved.

AP72202

Application Information (continued)

H-Bridge Controller (continued)

The regulator enters PFM as the output load decreases when the valley of the inductor current is less than 0. The zero cross detection will be

activated after 40µs delay before switching the mode from PWM to PFM. During PFM operation in buck mode, Switch Q3 is closed and Switch Q4

is open. Switches Q1 and Q2 operate in discontinuous mode during PFM operation until output voltage is approximately 1.2% upper threshold of

the PFM hysteretic controller. Then all switches are open to allow VOUT to decay until it reaches nominal regulation before switching again. This

operation will reduce switching losses at light load, thus improving efficiency. Likewise, the AP72202 closes Switch Q1 and Switch Q4 to ramp up

the current in the inductor during PFM operation in boost mode. When the inductor current reaches 1A, the device turns OFF Switch Q4, then turns

ON Switch Q3. With Switch Q3 closed, output voltage increases as the inductor current ramps down. When the loading current gets higher, there

will be multiple PFM pulses to charge up the output capacitor. These pulses continue until VOUT has achieved the 1.2% upper threshold of the PFM

hysteretic controller. Switching action then stops until VOUT decays until it reaches normal regulation before switching again. The regulator resumes

normal PWM operation as the output load increases and VOUT drops 2% below the regulation point.

Regulator MODE Control

The AP72202 has a MODE pin as well as I2C enable bit. Connecting MODE pin low sets the regulator to operate in PFM. Tying the MODE to VIN

sets the device in PWM. The MODE pin condition is set during the POR operation of the regulator and can only be overridden by the I2C. In the

address number 0x02, bit 6 and bit 0 are BB_UMODE and BB_FPWM respectively. These two bits can set the mode of operation of PFM, enhanced

ultrasonic, or forced PWM.

When the enhanced ultrasonic is set, this activates a unique pulse-skipping mode with a minimum switching frequency of 20kHz. An ultrasonic pulse

occurs when the regulator detects that no switching has occurred after 37µs. Once triggered, the ultrasonic pulse turns on the switch Q2 (buck mode)

or Q3 (boost mode) for approximately 50ns to induce a negative inductor current. This process continues until FB drops to the regulation point. Then

the regulator waits for the next clock edge to initiate the ON time. The table below is the truth table for the MODE operation found in I2C address

0x02.

BIT6

BIT0

Operating Mode

0

0

PFM

1

0

Ultrasonic Mode

x

1

PWM

Table 2. MODE Control Table

Power-Good (PG) Indicator

Buck-boost has an open-drain output that is actively held low during soft-start period until the output voltage reaches 80%. When the output voltage

is outside of its regulation by -20%, the PG will pull low until the output returns to set value. The PG low to high transition is delayed by 1.5ms while

the falling edge PG is delayed by 3µs to prevent false triggering. The polarity of PG output is programmable thru I2C in address 0x03 bit 4. It is active

high by default.

Overcurrent Protection

The AP72202 has an OCP pin as well as I2C enable bit to adjust the threshold 2.5A or 4.4A. The OCP pin control setting is the condition upon POR

operation of the regulator and can only be overridden by the I2C. The AP72202 detects the current limit on the high side, Q1, to protect the device

against overload or short-circuit conditions. The peak current in the switch is monitored cycle by cycle with comparator delay approximately 100ns

to guard against noise glitches. If the high side Q1 current limit is reached, the high side Q1 is turned off and the low side Q2 is turned on until the

switch current decreases below OC threshold. The frequency is reduced in order to protect the device from damage. The Q1 peak current limit

remains active during this state. After 17 consecutive cycles in OCP event, the regulator enters hiccup mode where all power FETs are turned off

and wait for 15ms before attempt to restart.

Reverse Current Protection

During fixed-frequency operation, a reverse current comparator on switch Q2 monitors the current entering VOUT. When this current exceeds 2A

(typical), switch Q2 will be turned off for the remainder of the switching cycle. This feature protects the buck-boost converter from excessive reverse

current if the buck-boost output is held above the regulation voltage by an external source.

Undervoltage Lockout

The undervoltage lockout (UVLO) feature prevents abnormal operation in the event that the supply voltage is too low to guarantee proper operation.

When the VIN voltage falls below the UVLO threshold, the regulator is disabled.

16