TMS320DM355 datasheet(132/153 Pages) TI

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SPI_CLK

(ClockPolarity=0)

SPI_CLK

(ClockPolarity=1)

SPI_DI

(Input)

SPI_DO

(Output)

MSBIN

DATA

LSBIN

LSBOUT

MSBOUT

DATA

SPI_EN

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463 – SEPTEMBER 2007

Table 5-29. Timing Requirements for SPI Master Mode [Clock Phase = 0] (1)(see Figure 5-37)

DM355

NO.

UNIT

MIN

MAX

Setup time, SPI_DI (input) valid before SPI_CLK (output)

tsu(DIV-CLKL)

Clock Polarity = 0

.5P + 3

falling edge

Setup time, SPI_DI (in put) valid before SPI_CLK (output)

tsu(DIV-CLKH)

Clock Polarity = 1

.5P + 3

rising edge

Hold time, SPI_DI (input) valid after SPI_CLK (output) falling

th(CLKL-DIV)

Clock Polarity = 0

.5P + 3

edge

Hold time, SPI_DI (input) valid after SPI_CLK (output) rising

th(CLKH-DIV)

Clock Polarity = 1

2.5P + 3

edge

(1)

P = Period of the SPI module clock in nanoseconds (P = PLL1/6).

Table 5-30. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode

[Clock Phase = 0] (see Figure 5-37)

DM355

NO.

PARAMETER

UNIT

MIN

MAX

Delay time, SPI_CLK (output) rising edge to SPI_DO

td(CLKH-DOV)

Clock Polarity = 0

-4

(output) transition

Delay time, SPI_CLK (output) falling edge to SPI_DO

td(CLKL-DOV)

Clock Polarity = 1

-4

(output) transition

Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or falling

td(ENL-CLKH/L)

2P(1)

(1)

edge

P+.5C(2

td(CLKH/L-ENH)

Delay time, SPI_CLK (output) rising or falling edge to SPI_EN[1:0] (output) rising edge

(2)

)

(1)

The delay time can be adjusted using the SPI module register C2TDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface

(SPI) User's Guide (SPRUED4).

(2)

The delay time can be adjusted using the SPI module register T2CDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface

(SPI) User's Guide (SPRUED4).

Figure 5-37. SPI Master Mode External Timing (Clock Phase = 0)

SPI Master Mode Timings (Clock Phase = 1)

Peripheral Information and Electrical Specifications

132

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