Electronic Components Datasheet Search
  English  ▼

X  

PM7347 Datasheet(PDF) 216 Page - PMC-Sierra, Inc

Part # PM7347
Description  SATURN USER NETWORK INTERFACE for J2/E3/T3
PDF  341 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7347 Datasheet(HTML) 216 Page - PMC-Sierra, Inc

Back Button PM7347 Datasheet HTML 212Page - PMC-Sierra, Inc PM7347 Datasheet HTML 213Page - PMC-Sierra, Inc PM7347 Datasheet HTML 214Page - PMC-Sierra, Inc PM7347 Datasheet HTML 215Page - PMC-Sierra, Inc PM7347 Datasheet HTML 216Page - PMC-Sierra, Inc PM7347 Datasheet HTML 217Page - PMC-Sierra, Inc PM7347 Datasheet HTML 218Page - PMC-Sierra, Inc PM7347 Datasheet HTML 219Page - PMC-Sierra, Inc PM7347 Datasheet HTML 220Page - PMC-Sierra, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 216 / 341 page
background image
S/UNI®-JET Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
216
Document ID: PMC-1990267, Issue 3
Register 383H: TXCP-50 Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
R/W
TPRTYE
0
Bit 6
R/W
FOVRE
0
Bit 5
R/W
TSOCE
0
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R
TPRTYI
X
Bit 1
R
FOVRI
X
Bit 0
R
TSOCI
X
TSOCI
The TSOCI bit is set high when the TSOC input is sampled high during any position other
than the first word of the selected data structure. The write address counter is reset to the first
word of the data structure when TSOC is sampled high. This bit is reset immediately after a
read to this register.
FOVRI
The FOVRI bit is set high when an attempt is made to write into the FIFO when it is already
full. This bit is reset immediately after a read to this register
TPRTYI
The TPRTYI bit indicates if a parity error was detected on the TDAT input bus. When logic
one, the TPRTYI bit indicates a parity error over the active TDAT bus. The active TDAT bus
is TDAT[15:0] when ATM8 is tied low and is TDAT[7:0] when ATM8 is tied high. This bit is
cleared when this register is read. Odd or even parity is selected using the TPTYPE bit.
TSOCE
The TSOCE bit enables the generation of an interrupt when the TSOC input is sampled high
during any position other than the first word of the selected data structure. When TSOCE is
set to logic one, the interrupt is enabled.
FOVRE
The FOVRE bit enables the generation of an interrupt due to an attempt to write the FIFO
when it is already full. When FOVRE is set to logic one, the interrupt is enabled.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com