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PM7347 Datasheet(PDF) 216 Page - PMC-Sierra, Inc |
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PM7347 Datasheet(HTML) 216 Page - PMC-Sierra, Inc |
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216 / 341 page ![]() S/UNI®-JET Data Sheet Released Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 216 Document ID: PMC-1990267, Issue 3 Register 383H: TXCP-50 Interrupt Enable/Status Bit Type Function Default Bit 7 R/W TPRTYE 0 Bit 6 R/W FOVRE 0 Bit 5 R/W TSOCE 0 Bit 4 Unused X Bit 3 Unused X Bit 2 R TPRTYI X Bit 1 R FOVRI X Bit 0 R TSOCI X TSOCI The TSOCI bit is set high when the TSOC input is sampled high during any position other than the first word of the selected data structure. The write address counter is reset to the first word of the data structure when TSOC is sampled high. This bit is reset immediately after a read to this register. FOVRI The FOVRI bit is set high when an attempt is made to write into the FIFO when it is already full. This bit is reset immediately after a read to this register TPRTYI The TPRTYI bit indicates if a parity error was detected on the TDAT input bus. When logic one, the TPRTYI bit indicates a parity error over the active TDAT bus. The active TDAT bus is TDAT[15:0] when ATM8 is tied low and is TDAT[7:0] when ATM8 is tied high. This bit is cleared when this register is read. Odd or even parity is selected using the TPTYPE bit. TSOCE The TSOCE bit enables the generation of an interrupt when the TSOC input is sampled high during any position other than the first word of the selected data structure. When TSOCE is set to logic one, the interrupt is enabled. FOVRE The FOVRE bit enables the generation of an interrupt due to an attempt to write the FIFO when it is already full. When FOVRE is set to logic one, the interrupt is enabled. |
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