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PM7347 Datasheet(PDF) 230 Page - PMC-Sierra, Inc |
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PM7347 Datasheet(HTML) 230 Page - PMC-Sierra, Inc |
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230 / 341 page  S/UNI®-JET Data Sheet Released Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 230 Document ID: PMC-1990267, Issue 3 Register 398H: RBOC Configuration/Interrupt Enable Bit Type Function Default Bit 7 Unused X Bit 6 Unused X Bit 5 Unused X Bit 4 Unused X Bit 3 Unused X Bit 2 R/W IDLE 0 Bit 1 R/W AVC 0 Bit 0 R/W FEACE 0 FEACE The FEACE bit enables the generation of an interrupt when a valid FEAC(FEAC) code is detected. When a logic one is written to FEACE, the interrupt generation is enabled. AVC The AVC bit position selects the validation criterion used in determining a valid FEAC code. When a logic zero is written to AVC, a FEAC code is validated when eight out of the last 10 received codes are identical. The FEAC code is removed when 2 out of the last 10 received code do not match the validated code. When a logic one is written to AVC, a FEAC code is validated when four out of the last five received codes are identical. The FEAC code is removed when a single received FEACs does not match the validated code. IDLE The IDLE bit enables the generation of an interrupt when a validated FEAC is removed. When a logic one is written to IDLE, the interrupt generation is enabled. |
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