PM7347 datasheet(237/341 Pages) PMC

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S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

237

Document ID: PMC-1990267, Issue 3

Bit

Type

Function

Default

Bit 7

R/W

PDR[1]

Bit 6

R/W

PDR[0]

Bit 5

R/W

QRSS

Bit 4

R/W

Bit 3

R/W

TINV

Bit 2

R/W

RINV

Bit 1

R/W

AUTOSYNC

Bit 0

R/W

MANSYNC

PDR[1:0]

The PDR[1:0] bits select the content of the four pattern detector registers (at addresses xACH

to xAFH) to be any one of the pattern receive registers, the error count holding registers, or

the bit count holding registers. The selection is shown in Table 25:

Table 25 PRGD Pattern Detector Register Configuration

PDR[1:0]

PDR#1

PDR#2

PDR#3

PDR#4

00, 01

Pattern Receive (LSB)

Pattern Receive

Pattern Receive (MSB)

Error Count (LSB)

Error Count

Error Count (MSB)

Bit Count (LSB)

Bit Count

Bit Count(MSB)

QRSS

The QRSS bit enables the zero suppression feature required when generating the QRSS

sequence. When QRSS is a logic one, a one is forced in the TDATO stream when the

following 14 bit positions are all zeros. When QRSS is a logic zero, the zero suppression

feature is disabled.

The PS bit selects the generated pattern. When PS is a logic one, a repetitive pattern is

generated. When PS is a logic zero, a pseudo-random pattern is generated.

The PS bit must be programmed to the desired setting before programming any other PRGD

registers, or the transmitted pattern may be corrupted. Any time the setting of the PS bit is

changed, the rest of the PRGD registers should be reprogrammed.

TINV

The TINV bit controls the logical inversion of the generated data stream. When TINV is a

logic one, the data is inverted. When TINV is a logic zero, the data is not inverted

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