PM7347 datasheet(277/341 Pages) PMC

277 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

277

Document ID: PMC-1990267, Issue 3

In the transmit direction, the HCSB bit in the TXCP-50 Configuration 1 Register determines

whether the HCS is calculated internally or is inserted directly from Word 5. For the 52-byte word

structure, if the HCSB bit in the TXCP-50 is logic one, then no HCS byte is inserted and the

TXCP-50 will only transmit the data present on the 52 words. In such a configuration, the RXCP-

50 should be configured to pass the 52-byte word output without requiring cell delineation by

setting the CCDIS bit to logic one. This setting is useful for passing arbitrary payload through the

transmit and receive Utopia interfaces.

13.9

Resetting the RXFF and TXFF FIFOs

Resetting the receive and transmit FIFOs can be accomplished using the FIFORST bits (RXCP-

50 FIFO/UTOPIA Control & Configuration, TXCP-50 Configuration 1 Registers). When

resetting, the FIFORST bit should be written with a logic one, and held for two or more clock

cycles (the longer of two Utopia clock cycles or 16 line clock cycles). After de-asserting

FIFORST, data can be safely written to the TXFF after two or more clock cycles have passed.

13.10 Servicing Interrupts

The S/UNI-JET will assert INTB to logic zero when a condition that is configured to produce an

interrupt occurs. To determine the condition that caused this interrupt to occur, follow the

procedure below:

• Read the INT bits of the S/UNI-JET Clock Activity Monitor and Interrupt Identification

• Read the S/UNI-JET Interrupt Status Register (005H, 105H, 205H, and 305H) to identify

which block produced the interrupt. For example, a logic one on the TDPRI register bit in

• Service the interrupt.

• If the INTB pin is still logic zero, then there are still interrupts to be serviced. Otherwise, all

interrupts have been serviced. Wait for the next assertion of INTB.

13.11 Using the Performance Monitoring Features

The PMON and CPPM blocks are provided for performance monitoring purposes. The RXCP-50

and TXCP-50 also contain performance monitor registers. The PMON block is used to monitor

DS3, E3, and J2 performance primitives while the CPPM is used to monitor PLCP and idle-cell-

based primitives. The RXCP-50 is used to monitor received cell primitives, and the TXCP-50 is

used to monitor transmit cell primitives. The counters in the PMON block have been sized as not

to saturate if polled every second. The counters in the CPPM blocks have been sized as not to

saturate if polled every 1/2 second at line rates up to 44.736 MHz. The counters in the RXCP-50

and TXCP-50 have been sized to not saturate if polled every second at line rates up to 44.736

MHz.

PM7347 Datasheet(PDF) 277 Page - PMC-Sierra, Inc