PM7347 datasheet(281/341 Pages) PMC

281 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

281

Document ID: PMC-1990267, Issue 3

Polling Mode

The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO.

The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable

Upper Transmit Threshold. The CRC bit can be set to logic one so that the FCS is generated and

inserted at the end of a packet. The TDPR Lower Interrupt Threshold should be set to such a

value that sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE

bits are all set to logic zero since packet transmission is set to work with a periodic polling

procedure.

To transmit HDLC packets:

• Wait until data is available to be transmitted, then go to step 2.

• Read the TDPR Interrupt Status Register.

• If FULL=1, then the TDPR FIFO is full and no further bytes can be written. Continue polling

the TDPR Interrupt Status Register until either FULL=0 or BLFILL=1. Then, go to either

step 4 or 5 depending on implementation preference.

• If BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. Write the data

into the TDPR Transmit Data Register. Go to step 6.

• If FULL=0, then the TDPR FIFO has room for at least 1 more byte to be written. Write the

data into the TDPR Transmit Data Register. Go to step 6.

• If more data bytes are to be transmitted in the packet, then go to step 2.

• If all bytes in the packet have been sent, then set the EOM bit in the TDPR Configuration

13.13 Using the Internal Data Link Receiver

Note: The access rate to the RDLC Registers is limited by the rate of the internal high-speed

system clock selected by the LINESYSCLK register bit of the S/UNI-JET Miscellaneous

Registers (09BH, 19BH, 29BH, 39BH). Consecutive accesses to the RDLC Status and RDLC

Data Registers should be accessed at a rate no faster than 1/10 that of the selected RDLC high-

speed system clock. This time is used by the high-speed system clock to sample the event and

update the FIFO status. Instantaneous variations in the high-speed reference clock frequencies

(e.g. jitter in the receive line clock) must be considered when determining the procedure used to

read RDLC Registers.

On power up of the system, the RDLC should be disabled by setting the EN bit in the

Configuration Register to logic zero (default state). The RDLC Interrupt Control Register should

then be initialized to enable the INT output and to select the FIFO buffer fill level at which an

interrupt will be generated. If the INTE bit is not set to logic one, the RDLC Status Register must

be continuously polled to check the interrupt status (INTR) bit.

PM7347 Datasheet(PDF) 281 Page - PMC-Sierra, Inc