PM7347 datasheet(282/341 Pages) PMC

282 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

282

Document ID: PMC-1990267, Issue 3

After the RDLC Interrupt Control Register has been written, the RDLC can be enabled at any

time by setting the EN bit in the RDLC Configuration Register to logic one. When the RDLC is

enabled, it will assume the link status is idle (all ones) and immediately begin searching for flags.

When the first flag is found, an interrupt will be generated, and a dummy byte will be written into

the FIFO buffer, which provides alignment of link up status with the data read from the FIFO.

When an abort character is received, another dummy byte and link down status is written into the

FIFO, which provides alignment of link down status with the data read from the FIFO. It is up to

the controlling processor to check the COLS bit in the RDLC Status Register for a change in the

link status. If the COLS bit is set to logic one, the FIFO must be emptied to determine the current

link status. The first flag and abort status encoded in the PBS bits are used to set and clear a Link

Active software flag.

When the last byte of a properly terminated packet is received, an interrupt is generated. While

the RDLC Status Register is being read the PKIN bit will be logic one. This can be a signal to the

external processor to empty the bytes remaining in the FIFO or to just increment a number-of-

packets-received count and wait for the FIFO to fill to a programmable level. Once the RDLC

Status Register is read, the PKIN bit is cleared to logic zero. If this register is read immediately

after the last packet byte is read from the FIFO, the PBS[2] bit will be logic one and the CRC and

non-integer byte status can be checked by reading the PBS[1:0] bits.

When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must be emptied to

remove this source of interrupt.

The RDLC can be used in a polled or interrupt driven mode for the transfer of frame data. In the

polled mode, the processor controlling the RDLC must periodically read the RDLC Status

processor controlling the RDLC uses the S/UNI-JET INTB output, the S/UNI-JET Clock Activity

Monitor and Interrupt Identification Register, and the S/UNI-JET Interrupt Status Registers to

determine when to read the RDLC Data Register.

In the case of interrupt driven data transfer from the RDLC to the processor, the INTB output of

the S/UNI-JET is connected to the interrupt input of the processor. The processor interrupt service

routine verifies what block generated the interrupt by reading the S/UNI-JET Clock Activity

Monitor and Interrupt Identification Register, and the S/UNI-JET Interrupt Status Registers. Once

it has identified that the RDLC has generated the interrupt, it processes the data in the following

order:

• Reads the RDLC Status Register. The INTR bit should be logic one.

° If OVR = 1, then discards last frame and go to step 1. Overrun causes a reset of FIFO

pointers. Any packets that may have been in the FIFO are lost.

° If COLS = 1, then sets the EMPTY FIFO software flag.

° If PKIN = 1, increments the PACKET COUNT. If the FIFO is desired to be emptied as

soon as a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY

FIFO software flag is not set, FIFO emptying will delayed until the FIFO fill level is

exceeded.

• Reads the RDLC Data Register.

• Reads the RDLC Status Register.

PM7347 Datasheet(PDF) 282 Page - PMC-Sierra, Inc

PM7347 Datasheet(HTML) 282 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL