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PM7347 Datasheet(PDF) 284 Page - PMC-Sierra, Inc |
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PM7347 Datasheet(HTML) 284 Page - PMC-Sierra, Inc |
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284 / 341 page ![]() S/UNI®-JET Data Sheet Released Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 284 Document ID: PMC-1990267, Issue 3 Figure 20 Typical Data Frame 87 654 32 1 01 111 11 0 FLAG Address (high) (low) CONTROL Frame Check Sequence 01 111 11 0 FLAG data bytes written to the Transmit Data Register and serially transm itted, bit 1 first BIT: appended after EOM is set, if CRC is set Bit 1 is the first serial bit to be received. When enabled, the primary, secondary and universal addresses are compared with the high order packet address to determine a match. Figure 21 shows the timing of interrupts, the state of the FIFO, and the state of the Data Link relative the input data sequence. The cause of each interrupt and the processing required at each point is described in the following paragraphs. Figure 21 Example Multi-Packet Operational Sequence DATA INT FE LA 12 3 4 5 6 7 F F F FA D D D DD D D D D DDDD D F F F FD D D DF F Notes 1. F is the flag sequence (01111110). 2. A is the abort sequence (01111111). 3. D is the packet data bytes. 4. INT is the active high interrupt output. |
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