PM7347 datasheet(107/341 Pages) PMC

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S/UNI®-JET Data Sheet

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

107

Document ID: PMC-1990267, Issue 3

FIXSTUFF

The FIXSTUFF bit controls the transmit PLCP frame octet/nibble stuffing used for DS3 and

G.751 E3 PLCP frame formats. When a logic zero is written to FIXSTUFF, stuffing is

determined by the REF8KI input. When a logic one is written to FIXSTUFF and the DS3

PLCP frame format is enabled, a nibble is stuffed into the 13 nibble trailer twice every three

stuff opportunities (i.e. 13, 14, 14 nibbles). This stuff ratio provides for a nominal PLCP

frame rate of 125.0002366 µs (an error of 1.9 ppm). When the G.751 E3 PLCP frame format

is enabled, 18, 19 or 20 octets are stuffed into the trailer depending on the alignment of the

G.751 E3 frame, and the G.751 E3 PLCP frame. This yields a nominal PLCP frame rate of

125 µs.

M2TYPE

The M2TYPE bit selects the type of code transmitted in the M2 octet. These codes are

required in systems implementing the IEEE-802.6 DQDB protocol. When a logic zero is

written to M2TYPE, the fixed pattern type 0 code is transmitted in the M2 octet. When a

logic one is written to M2TYPE, the 1023 cyclic code pattern (starting with B6 hexadecimal

and ending with 8D hexadecimal) is transmitted in the M2 octet. Please refer to

TA-TSY-000772, Issue 3 and Supplement 1, for details on the codes.

M1TYPE

The M1TYPE bit selects the type of code transmitted in the M1 octet. These codes are

required in systems implementing the IEEE-802.6 DQDB protocol. When a logic zero is

written to M1TYPE, the fixed pattern type 0 code is transmitted in the M1 octet. When a

logic one is written to M1TYPE, the 1023 cyclic code pattern (starting with B6 hexadecimal

and ending with 8D hexadecimal) is transmitted in the M1 octet. Please refer to

TA-TSY-000772, Issue 3 and Supplement 1, for details on the codes.

FORM[1:0]

When EXT = 0 and PLCPEN = 0, the FORM[1:0] bits and the TFRM[1:0] bits in the S/UNI-

JET Transmit Configuration Register select the ATM direct-mapped transmission frame

format as shown below. When EXT = 0 and PLCPEN = 1, the FORM[1:0] bits along with the

TFRM[1:0] bits select the transmission and PLCP frame format as shown below. When EXT

= 1 and TOCTA = 1, then the FORM[1:0] bits control the cell alignment with respect to the

transmission overhead given on TIOHM as shown in Table 13. The FORM bits have no effect

if EXT = 1 and TOCTA = 0.

Table 13 SPLT FORM[1:0] Configurations

FORM[1]

FORM[0]

PLCP or ATM direct-mapped Framing Format /

Cell alignment

00DS3 / nibble

E3 or J2 / byte

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