PM7347 datasheet(132/341 Pages) PMC

132 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

132

Document ID: PMC-1990267, Issue 3

AISONES

The AISONES bit controls the pattern used to detect the AIS (AIS) when both AISPAT and

AISC bits in DS3 FRMR Configuration Register are logic zero; if either AISPAT or AISC are

logic one, the AISONES bit is ignored. When a logic zero is written to AISONES, the

algorithm checks that a framed all-ones payload pattern (1111..) signal is observed for a

period of time before declaring AIS. Only the payload bits are observed to follow an all-ones

pattern, the overhead bits (X, P, M, F, C) are ignored. When a logic one is written to

AISONES, the algorithm checks that an unframed all-ones pattern (1111..) signal is observed

for a period of time before declaring AIS. In this case all the bits, including the overhead, are

observed to follow an all-ones pattern. The valid combinations of AISPAT, AISC, and

AISONES bits are summarized in Table 15:

Table 15 DS3 FRMR AIS Configurations

AISPAT

AISC

AISONES

AIS Detected

Framed DS3 stream containing repeating 1010… pattern;

overhead bits ignored.

Framed DS3 stream containing C-bits all logic zero; payload

bits ignored.

Framed DS3 stream containing repeating 1010… pattern in

the payload, C-bits all logic zero, and X-bits=1. This can be

detected by setting both AISPAT and AISC high, and

declaring AIS only when AISV=1 and FERFV=0 (Register

x33H).

Framed DS3 stream containing all-ones payload pattern;

overhead bits ignored.

Unframed all-ones DS3 stream.

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