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PM7347 Datasheet(PDF) 137 Page - PMC-Sierra, Inc |
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PM7347 Datasheet(HTML) 137 Page - PMC-Sierra, Inc |
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137 / 341 page ![]() S/UNI®-JET Data Sheet Released Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 137 Document ID: PMC-1990267, Issue 3 Register 334H: DS3 TRAN Configuration Bit Type Function Default Bit 7 R/W CBTRAN 0 Bit 6 R/W AIS 0 Bit 5 R/W IDL 0 Bit 4 R/W FERF 0 Bit 3 R/W Reserved 0 Bit 2 Unused X Bit 1 Unused X Bit 0 R/W CBIT 0 CBIT The CBIT bit enables the DS3 C-bit parity application. When CBIT is written with a logic one, C-bit parity is enabled, and the S/UNI-JET modifies the C-bits as required to include the path maintenance data link, the FEAC channel, the FEBE indication, and the path parity. When CBIT is written with a logic zero, the M23 application is selected, and each C-bit is set to logic one by the S/UNI-JET except for the first C-bit of the frame, which is forced to toggle every frame. Note: The C-bits may be modified as required using the DS3 overhead access port (TOH) regardless of the setting of this bit. FERF The FERF bit enables insertion of the far end receive failure maintenance signal in the DS3 stream. When FERF is written with a logic one, the X1 and X2 overhead bit positions are set to logic zero. When FERF is written with a logic zero, the X1 and X2 overhead bit positions in the DS3 stream are set to logic one. IDL The IDL bit enables insertion of the idle maintenance signal in the DS3 stream. When IDL is written with a logic one, the DS3 payload is overwritten with the repeating pattern 1100.. The DS3 overhead bit insertion (X, P, M F, and C) continues normally. When IDL is written with a logic zero, the idle signal is not inserted. AIS The AIS bit enables insertion of the AIS maintenance signal in the DS3 stream. When AIS is written with a logic one, the DS3 payload is overwritten with the repeating pattern 1010.. The DS3 overhead bit insertion (X, P, M and F) continues normally. The values inserted in the C- bits during AIS transmission are controlled by the CBTRAN bit in this register. When AIS is written with a logic zero, the AIS signal is not inserted. |
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