PM7347 datasheet(183/341 Pages) PMC

183 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

183

Document ID: PMC-1990267, Issue 3

Bit

Type

Function

Default

Bit 7

R/W

FLGSHARE

Bit 6

R/W

FIFOCLR

Bit 5

R/W

Reserved

Bit 4

Unused

Bit 3

R/W

EOM

Bit 2

R/W

ABT

Bit 1

R/W

CRC

Bit 0

R/W

Consecutive writes to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and TDPR

Transmit Data Register and reads of the TDPR Interrupt Status/UDR Clear Register should not

occur at rates greater than 1/8th that of the clock selected by the LINESYSCLK bit of the S/UNI-

JET Miscellaneous Register (39BH).

The EN bit enables the TDPR functions. When EN is set to logic one, the TDPR is enabled

and flag sequences are sent until data is written into the TDPR Transmit Data Register. When

the EN bit is set to logic zero, the TDPR is disabled and an all-ones Idle sequence is

transmitted on the datalink.

CRC

The CRC enable bit controls the generation of the CCITT_CRC frame check sequence (FCS).

Setting the CRC bit to logic one enables the CCITT-CRC generator and appends the 16-bit

FCS to the end of each message. When the CRC bit is set to logic zero, the FCS is not

appended to the end of the message. The CRC type used is the CCITT-CRC with generator

polynomial x16 + x12 + x5 + 1. The high order bit of the FCS word is transmitted first.

ABT

The Abort (ABT) bit controls the sending of the seven consecutive-ones HDLC abort code.

Setting the ABT bit to a logic one causes the 01111111 code (the 0 is transmitted first) to be

transmitted after the current byte from the TDPR FIFO is transmitted. The TDPR FIFO is

then reset. All data in the TDPR FIFO will be lost. Aborts are continuously sent and the FIFO

is held in reset until this bit is reset to a logic zero. At least one Abort sequence will be sent

when the ABT bit transitions from logic zero to logic one.

PM7347 Datasheet(PDF) 183 Page - PMC-Sierra, Inc

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